include/fsl_mmdc.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef FSL_MMDC_H
   8 #define FSL_MMDC_H
   9
  10 /* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
  11 #define MPWLGCR_HW_WL_EN                (1 << 0)
  12
  13 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
  14 #define MPPDCMPR2_MPR_COMPARE_EN        (1 << 0)
  15
  16
  17 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
  18 #define AUTO_RD_DQS_GATING_CALIBRATION_EN       (1 << 28)
  19
  20 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
  21 #define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN      (1 << 4)
  22
  23 /* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
  24 #define MMDC_MAPSR_PWR_SAV_CTRL_STAT    0x00001067
  25
  26 /* MMDC Core Refresh Control Register (MMDC_MDREF) */
  27 #define MDREF_START_REFRESH     (1 << 0)
  28
  29 /* MMDC Core Special Command Register (MDSCR) */
  30 #define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
  31 #define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
  32 #define MDSCR_DISABLE_CFG_REQ   (0 << 15)
  33 #define MDSCR_ENABLE_CON_REQ    (1 << 15)
  34 #define MDSCR_CON_ACK           (1 << 14)
  35 #define MDSCR_WL_EN             (1 << 9)
  36 #define CMD_NORMAL              (0 << 4)
  37 #define CMD_PRECHARGE           (1 << 4)
  38 #define CMD_AUTO_REFRESH        (2 << 4)
  39 #define CMD_LOAD_MODE_REG       (3 << 4)
  40 #define CMD_ZQ_CALIBRATION      (4 << 4)
  41 #define CMD_PRECHARGE_BANK_OPEN (5 << 4)
  42 #define CMD_MRR                 (6 << 4)
  43 #define CMD_BANK_ADDR_0         0x0
  44 #define CMD_BANK_ADDR_1         0x1
  45 #define CMD_BANK_ADDR_2         0x2
  46 #define CMD_BANK_ADDR_3         0x3
  47 #define CMD_BANK_ADDR_4         0x4
  48 #define CMD_BANK_ADDR_5         0x5
  49 #define CMD_BANK_ADDR_6         0x6
  50 #define CMD_BANK_ADDR_7         0x7
  51
  52 /* MMDC Core Control Register (MDCTL) */
  53 #define MDCTL_SDE0              (1 << 31)
  54 #define MDCTL_SDE1              (1 << 30)
  55
  56 /* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
  57 #define MPZQHWCTRL_ZQ_HW_FORCE  (1 << 16)
  58
  59 /* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
  60 #define MMDC_MPMUR0_FRC_MSR     (1 << 11)
  61
  62 /* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
  63 /* default 64 for a quarter cycle delay */
  64 #define MMDC_MPRDDLCTL_DEFAULT_DELAY    0x40404040
  65
  66 /* MMDC Registers */
  67 struct mmdc_regs {
  68         u32 mdctl;
  69         u32 mdpdc;
  70         u32 mdotc;
  71         u32 mdcfg0;
  72         u32 mdcfg1;
  73         u32 mdcfg2;
  74         u32 mdmisc;
  75         u32 mdscr;
  76         u32 mdref;
  77         u32 res1[2];
  78         u32 mdrwd;
  79         u32 mdor;
  80         u32 mdmrr;
  81         u32 mdcfg3lp;
  82         u32 mdmr4;
  83         u32 mdasp;
  84         u32 res2[239];
  85         u32 maarcr;
  86         u32 mapsr;
  87         u32 maexidr0;
  88         u32 maexidr1;
  89         u32 madpcr0;
  90         u32 madpcr1;
  91         u32 madpsr0;
  92         u32 madpsr1;
  93         u32 madpsr2;
  94         u32 madpsr3;
  95         u32 madpsr4;
  96         u32 madpsr5;
  97         u32 masbs0;
  98         u32 masbs1;
  99         u32 res3[2];
 100         u32 magenp;
 101         u32 res4[239];
 102         u32 mpzqhwctrl;
 103         u32 mpzqswctrl;
 104         u32 mpwlgcr;
 105         u32 mpwldectrl0;
 106         u32 mpwldectrl1;
 107         u32 mpwldlst;
 108         u32 mpodtctrl;
 109         u32 mprddqby0dl;
 110         u32 mprddqby1dl;
 111         u32 mprddqby2dl;
 112         u32 mprddqby3dl;
 113         u32 mpwrdqby0dl;
 114         u32 mpwrdqby1dl;
 115         u32 mpwrdqby2dl;
 116         u32 mpwrdqby3dl;
 117         u32 mpdgctrl0;
 118         u32 mpdgctrl1;
 119         u32 mpdgdlst0;
 120         u32 mprddlctl;
 121         u32 mprddlst;
 122         u32 mpwrdlctl;
 123         u32 mpwrdlst;
 124         u32 mpsdctrl;
 125         u32 mpzqlp2ctl;
 126         u32 mprddlhwctl;
 127         u32 mpwrdlhwctl;
 128         u32 mprddlhwst0;
 129         u32 mprddlhwst1;
 130         u32 mpwrdlhwst0;
 131         u32 mpwrdlhwst1;
 132         u32 mpwlhwerr;
 133         u32 mpdghwst0;
 134         u32 mpdghwst1;
 135         u32 mpdghwst2;
 136         u32 mpdghwst3;
 137         u32 mppdcmpr1;
 138         u32 mppdcmpr2;
 139         u32 mpswdar0;
 140         u32 mpswdrdr0;
 141         u32 mpswdrdr1;
 142         u32 mpswdrdr2;
 143         u32 mpswdrdr3;
 144         u32 mpswdrdr4;
 145         u32 mpswdrdr5;
 146         u32 mpswdrdr6;
 147         u32 mpswdrdr7;
 148         u32 mpmur0;
 149         u32 mpwrcadl;
 150         u32 mpdccr;
 151 };
 152
 153 struct fsl_mmdc_info {
 154         u32 mdctl;
 155         u32 mdpdc;
 156         u32 mdotc;
 157         u32 mdcfg0;
 158         u32 mdcfg1;
 159         u32 mdcfg2;
 160         u32 mdmisc;
 161         u32 mdref;
 162         u32 mdrwd;
 163         u32 mdor;
 164         u32 mdasp;
 165         u32 mpodtctrl;
 166         u32 mpzqhwctrl;
 167         u32 mprddlctl;
 168 };
 169
 170 void mmdc_init(const struct fsl_mmdc_info *);
 171
 172 #endif /* FSL_MMDC_H */