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Commit | Line | Data |
---|---|---|
e2211743 | 1 | /* |
dc7c9a1a | 2 | * linux/include/linux/mtd/nand.h |
e2211743 | 3 | * |
2a8e0fc8 CH |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
e2211743 | 7 | * |
ff94bc40 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
e2211743 | 9 | * |
cfa460ad WJ |
10 | * Info: |
11 | * Contains standard defines and IDs for NAND flash devices | |
e2211743 | 12 | * |
cfa460ad WJ |
13 | * Changelog: |
14 | * See git changelog. | |
e2211743 WD |
15 | */ |
16 | #ifndef __LINUX_MTD_NAND_H | |
17 | #define __LINUX_MTD_NAND_H | |
18 | ||
b5bf5cb3 | 19 | #include <config.h> |
cfa460ad | 20 | |
b5bf5cb3 MY |
21 | #include <linux/compat.h> |
22 | #include <linux/mtd/mtd.h> | |
23 | #include <linux/mtd/flashchip.h> | |
24 | #include <linux/mtd/bbm.h> | |
addb2e16 BS |
25 | |
26 | struct mtd_info; | |
245eb900 | 27 | struct nand_flash_dev; |
ceee07b6 SW |
28 | struct device_node; |
29 | ||
addb2e16 | 30 | /* Scan and identify a NAND device */ |
6a1ff76e | 31 | int nand_scan(struct mtd_info *mtd, int max_chips); |
ff94bc40 HS |
32 | /* |
33 | * Separate phases of nand_scan(), allowing board driver to intervene | |
34 | * and override command or ECC setup according to flash type. | |
35 | */ | |
6a1ff76e | 36 | int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
ff94bc40 | 37 | struct nand_flash_dev *table); |
6a1ff76e | 38 | int nand_scan_tail(struct mtd_info *mtd); |
cfa460ad | 39 | |
addb2e16 | 40 | /* Free resources held by the NAND device */ |
6a1ff76e | 41 | void nand_release(struct mtd_info *mtd); |
addb2e16 | 42 | |
cfa460ad | 43 | /* Internal helper for board drivers which need to override command function */ |
6a1ff76e | 44 | void nand_wait_ready(struct mtd_info *mtd); |
addb2e16 | 45 | |
2a8e0fc8 CH |
46 | /* |
47 | * This constant declares the max. oobsize / page, which | |
addb2e16 BS |
48 | * is supported now. If you add a chip with bigger oobsize/page |
49 | * adjust this accordingly. | |
50 | */ | |
c1fe6b5b | 51 | #define NAND_MAX_OOBSIZE 1664 |
2580a2a7 | 52 | #define NAND_MAX_PAGESIZE 16384 |
addb2e16 BS |
53 | |
54 | /* | |
55 | * Constants for hardware specific CLE/ALE/NCE function | |
cfa460ad WJ |
56 | * |
57 | * These are bits which can be or'ed to set/clear multiple | |
58 | * bits in one go. | |
59 | */ | |
addb2e16 | 60 | /* Select the chip by setting nCE to low */ |
cfa460ad | 61 | #define NAND_NCE 0x01 |
addb2e16 | 62 | /* Select the command latch by setting CLE to high */ |
cfa460ad | 63 | #define NAND_CLE 0x02 |
addb2e16 | 64 | /* Select the address latch by setting ALE to high */ |
cfa460ad WJ |
65 | #define NAND_ALE 0x04 |
66 | ||
67 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
68 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
69 | #define NAND_CTRL_CHANGE 0x80 | |
addb2e16 | 70 | |
e2211743 WD |
71 | /* |
72 | * Standard NAND flash commands | |
73 | */ | |
74 | #define NAND_CMD_READ0 0 | |
75 | #define NAND_CMD_READ1 1 | |
cfa460ad | 76 | #define NAND_CMD_RNDOUT 5 |
e2211743 WD |
77 | #define NAND_CMD_PAGEPROG 0x10 |
78 | #define NAND_CMD_READOOB 0x50 | |
79 | #define NAND_CMD_ERASE1 0x60 | |
80 | #define NAND_CMD_STATUS 0x70 | |
81 | #define NAND_CMD_SEQIN 0x80 | |
cfa460ad | 82 | #define NAND_CMD_RNDIN 0x85 |
e2211743 WD |
83 | #define NAND_CMD_READID 0x90 |
84 | #define NAND_CMD_ERASE2 0xd0 | |
2a8e0fc8 | 85 | #define NAND_CMD_PARAM 0xec |
dfe64e2c SL |
86 | #define NAND_CMD_GET_FEATURES 0xee |
87 | #define NAND_CMD_SET_FEATURES 0xef | |
e2211743 WD |
88 | #define NAND_CMD_RESET 0xff |
89 | ||
2a8e0fc8 CH |
90 | #define NAND_CMD_LOCK 0x2a |
91 | #define NAND_CMD_UNLOCK1 0x23 | |
92 | #define NAND_CMD_UNLOCK2 0x24 | |
93 | ||
addb2e16 BS |
94 | /* Extended commands for large page devices */ |
95 | #define NAND_CMD_READSTART 0x30 | |
cfa460ad | 96 | #define NAND_CMD_RNDOUTSTART 0xE0 |
addb2e16 BS |
97 | #define NAND_CMD_CACHEDPROG 0x15 |
98 | ||
cfa460ad WJ |
99 | /* Extended commands for AG-AND device */ |
100 | /* | |
101 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
102 | * there is no way to distinguish that from NAND_CMD_READ0 | |
103 | * until the remaining sequence of commands has been completed | |
104 | * so add a high order bit and mask it off in the command. | |
105 | */ | |
106 | #define NAND_CMD_DEPLETE1 0x100 | |
107 | #define NAND_CMD_DEPLETE2 0x38 | |
108 | #define NAND_CMD_STATUS_MULTI 0x71 | |
109 | #define NAND_CMD_STATUS_ERROR 0x72 | |
110 | /* multi-bank error status (banks 0-3) */ | |
111 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
112 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
113 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
114 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
115 | #define NAND_CMD_STATUS_RESET 0x7f | |
116 | #define NAND_CMD_STATUS_CLEAR 0xff | |
117 | ||
118 | #define NAND_CMD_NONE -1 | |
119 | ||
addb2e16 BS |
120 | /* Status bits */ |
121 | #define NAND_STATUS_FAIL 0x01 | |
122 | #define NAND_STATUS_FAIL_N1 0x02 | |
123 | #define NAND_STATUS_TRUE_READY 0x20 | |
124 | #define NAND_STATUS_READY 0x40 | |
125 | #define NAND_STATUS_WP 0x80 | |
126 | ||
52cde35b BB |
127 | #define NAND_DATA_IFACE_CHECK_ONLY -1 |
128 | ||
addb2e16 BS |
129 | /* |
130 | * Constants for ECC_MODES | |
131 | */ | |
cfa460ad WJ |
132 | typedef enum { |
133 | NAND_ECC_NONE, | |
134 | NAND_ECC_SOFT, | |
135 | NAND_ECC_HW, | |
136 | NAND_ECC_HW_SYNDROME, | |
f83b7f9e | 137 | NAND_ECC_HW_OOB_FIRST, |
4c6de856 | 138 | NAND_ECC_SOFT_BCH, |
cfa460ad | 139 | } nand_ecc_modes_t; |
addb2e16 | 140 | |
dc7c9a1a | 141 | /* |
addb2e16 | 142 | * Constants for Hardware ECC |
cfa460ad | 143 | */ |
addb2e16 BS |
144 | /* Reset Hardware ECC for read */ |
145 | #define NAND_ECC_READ 0 | |
146 | /* Reset Hardware ECC for write */ | |
147 | #define NAND_ECC_WRITE 1 | |
dfe64e2c | 148 | /* Enable Hardware ECC before syndrome is read back from flash */ |
addb2e16 BS |
149 | #define NAND_ECC_READSYN 2 |
150 | ||
ceee07b6 SW |
151 | /* |
152 | * Enable generic NAND 'page erased' check. This check is only done when | |
153 | * ecc.correct() returns -EBADMSG. | |
154 | * Set this flag if your implementation does not fix bitflips in erased | |
155 | * pages and you want to rely on the default implementation. | |
156 | */ | |
157 | #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) | |
19d30ded | 158 | #define NAND_ECC_MAXIMIZE BIT(1) |
1fb87de8 MG |
159 | /* |
160 | * If your controller already sends the required NAND commands when | |
161 | * reading or writing a page, then the framework is not supposed to | |
162 | * send READ0 and SEQIN/PAGEPROG respectively. | |
163 | */ | |
164 | #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) | |
ceee07b6 | 165 | |
cfa460ad WJ |
166 | /* Bit mask for flags passed to do_nand_read_ecc */ |
167 | #define NAND_GET_DEVICE 0x80 | |
168 | ||
169 | ||
2a8e0fc8 CH |
170 | /* |
171 | * Option constants for bizarre disfunctionality and real | |
172 | * features. | |
173 | */ | |
dfe64e2c | 174 | /* Buswidth is 16 bit */ |
addb2e16 BS |
175 | #define NAND_BUSWIDTH_16 0x00000002 |
176 | /* Device supports partial programming without padding */ | |
177 | #define NAND_NO_PADDING 0x00000004 | |
178 | /* Chip has cache program function */ | |
179 | #define NAND_CACHEPRG 0x00000008 | |
180 | /* Chip has copy back function */ | |
181 | #define NAND_COPYBACK 0x00000010 | |
2a8e0fc8 | 182 | /* |
ff94bc40 HS |
183 | * Chip requires ready check on read (for auto-incremented sequential read). |
184 | * True only for small page devices; large page devices do not support | |
185 | * autoincrement. | |
2a8e0fc8 | 186 | */ |
ff94bc40 HS |
187 | #define NAND_NEED_READRDY 0x00000100 |
188 | ||
cfa460ad WJ |
189 | /* Chip does not allow subpage writes */ |
190 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
191 | ||
2a8e0fc8 CH |
192 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
193 | #define NAND_BROKEN_XD 0x00000400 | |
194 | ||
195 | /* Device behaves just like nand, but is readonly */ | |
196 | #define NAND_ROM 0x00000800 | |
addb2e16 | 197 | |
c788ecfd | 198 | /* Device supports subpage reads */ |
ff94bc40 | 199 | #define NAND_SUBPAGE_READ 0x00001000 |
c788ecfd | 200 | |
ceee07b6 SW |
201 | /* |
202 | * Some MLC NANDs need data scrambling to limit bitflips caused by repeated | |
203 | * patterns. | |
204 | */ | |
205 | #define NAND_NEED_SCRAMBLING 0x00002000 | |
206 | ||
addb2e16 | 207 | /* Options valid for Samsung large page devices */ |
ff94bc40 | 208 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
addb2e16 BS |
209 | |
210 | /* Macros to identify the above */ | |
addb2e16 | 211 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
c788ecfd | 212 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
1fb87de8 | 213 | #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) |
addb2e16 | 214 | |
addb2e16 | 215 | /* Non chip related options */ |
cfa460ad | 216 | /* This option skips the bbt scan during initialization. */ |
dfe64e2c | 217 | #define NAND_SKIP_BBTSCAN 0x00010000 |
2a8e0fc8 CH |
218 | /* |
219 | * This option is defined if the board driver allocates its own buffers | |
220 | * (e.g. because it needs them DMA-coherent). | |
221 | */ | |
dfe64e2c | 222 | #define NAND_OWN_BUFFERS 0x00020000 |
2a8e0fc8 | 223 | /* Chip may not exist, so silence any errors in scan */ |
dfe64e2c | 224 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
ff94bc40 HS |
225 | /* |
226 | * Autodetect nand buswidth with readid/onfi. | |
227 | * This suppose the driver will configure the hardware in 8 bits mode | |
228 | * when calling nand_scan_ident, and update its configuration | |
229 | * before calling nand_scan_tail. | |
230 | */ | |
231 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
ceee07b6 SW |
232 | /* |
233 | * This option could be defined by controller drivers to protect against | |
234 | * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers | |
235 | */ | |
236 | #define NAND_USE_BOUNCE_BUFFER 0x00100000 | |
2a8e0fc8 | 237 | |
addb2e16 | 238 | /* Options set by nand scan */ |
fb49454b SW |
239 | /* bbt has already been read */ |
240 | #define NAND_BBT_SCANNED 0x40000000 | |
cfa460ad WJ |
241 | /* Nand scan has allocated controller struct */ |
242 | #define NAND_CONTROLLER_ALLOC 0x80000000 | |
addb2e16 | 243 | |
cfa460ad WJ |
244 | /* Cell info constants */ |
245 | #define NAND_CI_CHIPNR_MSK 0x03 | |
246 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
ff94bc40 | 247 | #define NAND_CI_CELLTYPE_SHIFT 2 |
addb2e16 | 248 | |
addb2e16 BS |
249 | /* Keep gcc happy */ |
250 | struct nand_chip; | |
dc7c9a1a | 251 | |
ff94bc40 HS |
252 | /* ONFI features */ |
253 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
254 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
255 | ||
dfe64e2c SL |
256 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
257 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
258 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
259 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
260 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
261 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
262 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
263 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
264 | ||
265 | /* ONFI feature address */ | |
266 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
267 | ||
ff94bc40 HS |
268 | /* Vendor-specific feature address (Micron) */ |
269 | #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 | |
270 | ||
dfe64e2c SL |
271 | /* ONFI subfeature parameters length */ |
272 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
273 | ||
ff94bc40 HS |
274 | /* ONFI optional commands SET/GET FEATURES supported? */ |
275 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
276 | ||
0272c718 FF |
277 | struct nand_onfi_params { |
278 | /* rev info and features block */ | |
279 | /* 'O' 'N' 'F' 'I' */ | |
280 | u8 sig[4]; | |
281 | __le16 revision; | |
282 | __le16 features; | |
283 | __le16 opt_cmd; | |
ff94bc40 HS |
284 | u8 reserved0[2]; |
285 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
286 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
287 | u8 reserved1[17]; | |
0272c718 FF |
288 | |
289 | /* manufacturer information block */ | |
290 | char manufacturer[12]; | |
291 | char model[20]; | |
292 | u8 jedec_id; | |
293 | __le16 date_code; | |
294 | u8 reserved2[13]; | |
295 | ||
296 | /* memory organization block */ | |
297 | __le32 byte_per_page; | |
298 | __le16 spare_bytes_per_page; | |
299 | __le32 data_bytes_per_ppage; | |
300 | __le16 spare_bytes_per_ppage; | |
301 | __le32 pages_per_block; | |
302 | __le32 blocks_per_lun; | |
303 | u8 lun_count; | |
304 | u8 addr_cycles; | |
305 | u8 bits_per_cell; | |
306 | __le16 bb_per_lun; | |
307 | __le16 block_endurance; | |
308 | u8 guaranteed_good_blocks; | |
309 | __le16 guaranteed_block_endurance; | |
310 | u8 programs_per_page; | |
311 | u8 ppage_attr; | |
312 | u8 ecc_bits; | |
313 | u8 interleaved_bits; | |
314 | u8 interleaved_ops; | |
315 | u8 reserved3[13]; | |
316 | ||
317 | /* electrical parameter block */ | |
318 | u8 io_pin_capacitance_max; | |
319 | __le16 async_timing_mode; | |
320 | __le16 program_cache_timing_mode; | |
321 | __le16 t_prog; | |
322 | __le16 t_bers; | |
323 | __le16 t_r; | |
324 | __le16 t_ccs; | |
325 | __le16 src_sync_timing_mode; | |
ceee07b6 | 326 | u8 src_ssync_features; |
0272c718 FF |
327 | __le16 clk_pin_capacitance_typ; |
328 | __le16 io_pin_capacitance_typ; | |
329 | __le16 input_pin_capacitance_typ; | |
330 | u8 input_pin_capacitance_max; | |
ff94bc40 | 331 | u8 driver_strength_support; |
0272c718 | 332 | __le16 t_int_r; |
ceee07b6 SW |
333 | __le16 t_adl; |
334 | u8 reserved4[8]; | |
0272c718 FF |
335 | |
336 | /* vendor */ | |
ff94bc40 HS |
337 | __le16 vendor_revision; |
338 | u8 vendor[88]; | |
0272c718 FF |
339 | |
340 | __le16 crc; | |
ff94bc40 | 341 | } __packed; |
0272c718 FF |
342 | |
343 | #define ONFI_CRC_BASE 0x4F4E | |
344 | ||
ff94bc40 HS |
345 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
346 | struct onfi_ext_ecc_info { | |
347 | u8 ecc_bits; | |
348 | u8 codeword_size; | |
349 | __le16 bb_per_lun; | |
350 | __le16 block_endurance; | |
351 | u8 reserved[2]; | |
352 | } __packed; | |
353 | ||
354 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
355 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
356 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
357 | struct onfi_ext_section { | |
358 | u8 type; | |
359 | u8 length; | |
360 | } __packed; | |
361 | ||
362 | #define ONFI_EXT_SECTION_MAX 8 | |
363 | ||
364 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
365 | struct onfi_ext_param_page { | |
366 | __le16 crc; | |
367 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
368 | u8 reserved0[10]; | |
369 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
370 | ||
371 | /* | |
372 | * The actual size of the Extended Parameter Page is in | |
373 | * @ext_param_page_length of nand_onfi_params{}. | |
374 | * The following are the variable length sections. | |
375 | * So we do not add any fields below. Please see the ONFI spec. | |
376 | */ | |
377 | } __packed; | |
378 | ||
379 | struct nand_onfi_vendor_micron { | |
380 | u8 two_plane_read; | |
381 | u8 read_cache; | |
382 | u8 read_unique_id; | |
383 | u8 dq_imped; | |
384 | u8 dq_imped_num_settings; | |
385 | u8 dq_imped_feat_addr; | |
386 | u8 rb_pulldown_strength; | |
387 | u8 rb_pulldown_strength_feat_addr; | |
388 | u8 rb_pulldown_strength_num_settings; | |
389 | u8 otp_mode; | |
390 | u8 otp_page_start; | |
391 | u8 otp_data_prot_addr; | |
392 | u8 otp_num_pages; | |
393 | u8 otp_feat_addr; | |
394 | u8 read_retry_options; | |
395 | u8 reserved[72]; | |
396 | u8 param_revision; | |
397 | } __packed; | |
398 | ||
4e67c571 HS |
399 | struct jedec_ecc_info { |
400 | u8 ecc_bits; | |
401 | u8 codeword_size; | |
402 | __le16 bb_per_lun; | |
403 | __le16 block_endurance; | |
404 | u8 reserved[2]; | |
405 | } __packed; | |
406 | ||
407 | /* JEDEC features */ | |
408 | #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) | |
409 | ||
410 | struct nand_jedec_params { | |
411 | /* rev info and features block */ | |
412 | /* 'J' 'E' 'S' 'D' */ | |
413 | u8 sig[4]; | |
414 | __le16 revision; | |
415 | __le16 features; | |
416 | u8 opt_cmd[3]; | |
417 | __le16 sec_cmd; | |
418 | u8 num_of_param_pages; | |
419 | u8 reserved0[18]; | |
420 | ||
421 | /* manufacturer information block */ | |
422 | char manufacturer[12]; | |
423 | char model[20]; | |
424 | u8 jedec_id[6]; | |
425 | u8 reserved1[10]; | |
426 | ||
427 | /* memory organization block */ | |
428 | __le32 byte_per_page; | |
429 | __le16 spare_bytes_per_page; | |
430 | u8 reserved2[6]; | |
431 | __le32 pages_per_block; | |
432 | __le32 blocks_per_lun; | |
433 | u8 lun_count; | |
434 | u8 addr_cycles; | |
435 | u8 bits_per_cell; | |
436 | u8 programs_per_page; | |
437 | u8 multi_plane_addr; | |
438 | u8 multi_plane_op_attr; | |
439 | u8 reserved3[38]; | |
440 | ||
441 | /* electrical parameter block */ | |
442 | __le16 async_sdr_speed_grade; | |
443 | __le16 toggle_ddr_speed_grade; | |
444 | __le16 sync_ddr_speed_grade; | |
445 | u8 async_sdr_features; | |
446 | u8 toggle_ddr_features; | |
447 | u8 sync_ddr_features; | |
448 | __le16 t_prog; | |
449 | __le16 t_bers; | |
450 | __le16 t_r; | |
451 | __le16 t_r_multi_plane; | |
452 | __le16 t_ccs; | |
453 | __le16 io_pin_capacitance_typ; | |
454 | __le16 input_pin_capacitance_typ; | |
455 | __le16 clk_pin_capacitance_typ; | |
456 | u8 driver_strength_support; | |
ceee07b6 | 457 | __le16 t_adl; |
4e67c571 HS |
458 | u8 reserved4[36]; |
459 | ||
460 | /* ECC and endurance block */ | |
461 | u8 guaranteed_good_blocks; | |
462 | __le16 guaranteed_block_endurance; | |
463 | struct jedec_ecc_info ecc_info[4]; | |
464 | u8 reserved5[29]; | |
465 | ||
466 | /* reserved */ | |
467 | u8 reserved6[148]; | |
468 | ||
469 | /* vendor */ | |
470 | __le16 vendor_rev_num; | |
471 | u8 reserved7[88]; | |
472 | ||
473 | /* CRC for Parameter Page */ | |
474 | __le16 crc; | |
475 | } __packed; | |
476 | ||
addb2e16 | 477 | /** |
cfa460ad WJ |
478 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
479 | * @lock: protection lock | |
addb2e16 | 480 | * @active: the mtd device which holds the controller currently |
2a8e0fc8 CH |
481 | * @wq: wait queue to sleep on if a NAND operation is in |
482 | * progress used instead of the per chip wait queue | |
483 | * when a hw controller is available. | |
dc7c9a1a | 484 | */ |
addb2e16 | 485 | struct nand_hw_control { |
ff94bc40 HS |
486 | spinlock_t lock; |
487 | struct nand_chip *active; | |
cfa460ad WJ |
488 | }; |
489 | ||
490 | /** | |
dfe64e2c SL |
491 | * struct nand_ecc_ctrl - Control structure for ECC |
492 | * @mode: ECC mode | |
493 | * @steps: number of ECC steps per page | |
494 | * @size: data bytes per ECC step | |
495 | * @bytes: ECC bytes per step | |
496 | * @strength: max number of correctible bits per ECC step | |
497 | * @total: total number of ECC bytes per page | |
498 | * @prepad: padding information for syndrome based ECC generators | |
499 | * @postpad: padding information for syndrome based ECC generators | |
ceee07b6 | 500 | * @options: ECC specific options (see NAND_ECC_XXX flags defined above) |
cfa460ad | 501 | * @layout: ECC layout control struct pointer |
dfe64e2c SL |
502 | * @priv: pointer to private ECC control data |
503 | * @hwctl: function to control hardware ECC generator. Must only | |
cfa460ad | 504 | * be provided if an hardware ECC is available |
dfe64e2c | 505 | * @calculate: function for ECC calculation or readback from ECC hardware |
ceee07b6 SW |
506 | * @correct: function for ECC correction, matching to ECC generator (sw/hw). |
507 | * Should return a positive number representing the number of | |
508 | * corrected bitflips, -EBADMSG if the number of bitflips exceed | |
509 | * ECC strength, or any other error code if the error is not | |
510 | * directly related to correction. | |
511 | * If -EBADMSG is returned the input buffers should be left | |
512 | * untouched. | |
d3963721 SW |
513 | * @read_page_raw: function to read a raw page without ECC. This function |
514 | * should hide the specific layout used by the ECC | |
515 | * controller and always return contiguous in-band and | |
516 | * out-of-band data even if they're not stored | |
517 | * contiguously on the NAND chip (e.g. | |
518 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
519 | * out-of-band data). | |
520 | * @write_page_raw: function to write a raw page without ECC. This function | |
521 | * should hide the specific layout used by the ECC | |
522 | * controller and consider the passed data as contiguous | |
523 | * in-band and out-of-band data. ECC controller is | |
524 | * responsible for doing the appropriate transformations | |
525 | * to adapt to its specific layout (e.g. | |
526 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
527 | * out-of-band data). | |
dfe64e2c SL |
528 | * @read_page: function to read a page according to the ECC generator |
529 | * requirements; returns maximum number of bitflips corrected in | |
530 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
531 | * @read_subpage: function to read parts of the page covered by ECC; | |
532 | * returns same as read_page() | |
ff94bc40 | 533 | * @write_subpage: function to write parts of the page covered by ECC. |
dfe64e2c | 534 | * @write_page: function to write a page according to the ECC generator |
2a8e0fc8 | 535 | * requirements. |
dfe64e2c SL |
536 | * @write_oob_raw: function to write chip OOB data without ECC |
537 | * @read_oob_raw: function to read chip OOB data without ECC | |
cfa460ad WJ |
538 | * @read_oob: function to read chip OOB data |
539 | * @write_oob: function to write chip OOB data | |
540 | */ | |
541 | struct nand_ecc_ctrl { | |
2a8e0fc8 CH |
542 | nand_ecc_modes_t mode; |
543 | int steps; | |
544 | int size; | |
545 | int bytes; | |
546 | int total; | |
dfe64e2c | 547 | int strength; |
2a8e0fc8 CH |
548 | int prepad; |
549 | int postpad; | |
ceee07b6 | 550 | unsigned int options; |
cfa460ad | 551 | struct nand_ecclayout *layout; |
2a8e0fc8 CH |
552 | void *priv; |
553 | void (*hwctl)(struct mtd_info *mtd, int mode); | |
554 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
555 | uint8_t *ecc_code); | |
556 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
557 | uint8_t *calc_ecc); | |
558 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
dfe64e2c SL |
559 | uint8_t *buf, int oob_required, int page); |
560 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
81c77252 | 561 | const uint8_t *buf, int oob_required, int page); |
2a8e0fc8 | 562 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
dfe64e2c | 563 | uint8_t *buf, int oob_required, int page); |
2a8e0fc8 | 564 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
4e67c571 | 565 | uint32_t offs, uint32_t len, uint8_t *buf, int page); |
ff94bc40 HS |
566 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
567 | uint32_t offset, uint32_t data_len, | |
81c77252 | 568 | const uint8_t *data_buf, int oob_required, int page); |
dfe64e2c | 569 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
81c77252 | 570 | const uint8_t *buf, int oob_required, int page); |
dfe64e2c SL |
571 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
572 | int page); | |
573 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
574 | int page); | |
575 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
2a8e0fc8 CH |
576 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
577 | int page); | |
cfa460ad WJ |
578 | }; |
579 | ||
1fb87de8 MG |
580 | static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) |
581 | { | |
582 | return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); | |
583 | } | |
584 | ||
cfa460ad WJ |
585 | /** |
586 | * struct nand_buffers - buffer structure for read/write | |
4e67c571 HS |
587 | * @ecccalc: buffer pointer for calculated ECC, size is oobsize. |
588 | * @ecccode: buffer pointer for ECC read from flash, size is oobsize. | |
589 | * @databuf: buffer pointer for data, size is (page size + oobsize). | |
cfa460ad WJ |
590 | * |
591 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
592 | * consecutive order. | |
593 | */ | |
594 | struct nand_buffers { | |
b572595e SG |
595 | uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; |
596 | uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; | |
597 | uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, | |
598 | ARCH_DMA_MINALIGN)]; | |
cfa460ad | 599 | }; |
addb2e16 | 600 | |
01042499 SH |
601 | /** |
602 | * struct nand_sdr_timings - SDR NAND chip timings | |
603 | * | |
604 | * This struct defines the timing requirements of a SDR NAND chip. | |
605 | * These information can be found in every NAND datasheets and the timings | |
606 | * meaning are described in the ONFI specifications: | |
607 | * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing | |
608 | * Parameters) | |
609 | * | |
610 | * All these timings are expressed in picoseconds. | |
611 | * | |
6f84b26b BB |
612 | * @tBERS_max: Block erase time |
613 | * @tCCS_min: Change column setup time | |
614 | * @tPROG_max: Page program time | |
615 | * @tR_max: Page read time | |
01042499 SH |
616 | * @tALH_min: ALE hold time |
617 | * @tADL_min: ALE to data loading time | |
618 | * @tALS_min: ALE setup time | |
619 | * @tAR_min: ALE to RE# delay | |
620 | * @tCEA_max: CE# access time | |
621 | * @tCEH_min: CE# high hold time | |
622 | * @tCH_min: CE# hold time | |
623 | * @tCHZ_max: CE# high to output hi-Z | |
624 | * @tCLH_min: CLE hold time | |
625 | * @tCLR_min: CLE to RE# delay | |
626 | * @tCLS_min: CLE setup time | |
627 | * @tCOH_min: CE# high to output hold | |
628 | * @tCS_min: CE# setup time | |
629 | * @tDH_min: Data hold time | |
630 | * @tDS_min: Data setup time | |
631 | * @tFEAT_max: Busy time for Set Features and Get Features | |
632 | * @tIR_min: Output hi-Z to RE# low | |
633 | * @tITC_max: Interface and Timing Mode Change time | |
634 | * @tRC_min: RE# cycle time | |
635 | * @tREA_max: RE# access time | |
636 | * @tREH_min: RE# high hold time | |
637 | * @tRHOH_min: RE# high to output hold | |
638 | * @tRHW_min: RE# high to WE# low | |
639 | * @tRHZ_max: RE# high to output hi-Z | |
640 | * @tRLOH_min: RE# low to output hold | |
641 | * @tRP_min: RE# pulse width | |
642 | * @tRR_min: Ready to RE# low (data only) | |
643 | * @tRST_max: Device reset time, measured from the falling edge of R/B# to the | |
644 | * rising edge of R/B#. | |
645 | * @tWB_max: WE# high to SR[6] low | |
646 | * @tWC_min: WE# cycle time | |
647 | * @tWH_min: WE# high hold time | |
648 | * @tWHR_min: WE# high to RE# low | |
649 | * @tWP_min: WE# pulse width | |
650 | * @tWW_min: WP# transition to WE# low | |
651 | */ | |
652 | struct nand_sdr_timings { | |
6f84b26b BB |
653 | u64 tBERS_max; |
654 | u32 tCCS_min; | |
655 | u64 tPROG_max; | |
656 | u64 tR_max; | |
01042499 SH |
657 | u32 tALH_min; |
658 | u32 tADL_min; | |
659 | u32 tALS_min; | |
660 | u32 tAR_min; | |
661 | u32 tCEA_max; | |
662 | u32 tCEH_min; | |
663 | u32 tCH_min; | |
664 | u32 tCHZ_max; | |
665 | u32 tCLH_min; | |
666 | u32 tCLR_min; | |
667 | u32 tCLS_min; | |
668 | u32 tCOH_min; | |
669 | u32 tCS_min; | |
670 | u32 tDH_min; | |
671 | u32 tDS_min; | |
672 | u32 tFEAT_max; | |
673 | u32 tIR_min; | |
674 | u32 tITC_max; | |
675 | u32 tRC_min; | |
676 | u32 tREA_max; | |
677 | u32 tREH_min; | |
678 | u32 tRHOH_min; | |
679 | u32 tRHW_min; | |
680 | u32 tRHZ_max; | |
681 | u32 tRLOH_min; | |
682 | u32 tRP_min; | |
683 | u32 tRR_min; | |
684 | u64 tRST_max; | |
685 | u32 tWB_max; | |
686 | u32 tWC_min; | |
687 | u32 tWH_min; | |
688 | u32 tWHR_min; | |
689 | u32 tWP_min; | |
690 | u32 tWW_min; | |
691 | }; | |
692 | ||
693 | /** | |
694 | * enum nand_data_interface_type - NAND interface timing type | |
695 | * @NAND_SDR_IFACE: Single Data Rate interface | |
696 | */ | |
697 | enum nand_data_interface_type { | |
698 | NAND_SDR_IFACE, | |
699 | }; | |
700 | ||
701 | /** | |
702 | * struct nand_data_interface - NAND interface timing | |
703 | * @type: type of the timing | |
704 | * @timings: The timing, type according to @type | |
705 | */ | |
706 | struct nand_data_interface { | |
707 | enum nand_data_interface_type type; | |
708 | union { | |
709 | struct nand_sdr_timings sdr; | |
710 | } timings; | |
711 | }; | |
712 | ||
713 | /** | |
714 | * nand_get_sdr_timings - get SDR timing from data interface | |
715 | * @conf: The data interface | |
716 | */ | |
717 | static inline const struct nand_sdr_timings * | |
718 | nand_get_sdr_timings(const struct nand_data_interface *conf) | |
719 | { | |
720 | if (conf->type != NAND_SDR_IFACE) | |
721 | return ERR_PTR(-EINVAL); | |
722 | ||
723 | return &conf->timings.sdr; | |
724 | } | |
725 | ||
addb2e16 BS |
726 | /** |
727 | * struct nand_chip - NAND Private Flash Chip Data | |
ceee07b6 | 728 | * @mtd: MTD device registered to the MTD framework |
2a8e0fc8 CH |
729 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
730 | * flash device | |
731 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
732 | * flash device. | |
42bd19ce | 733 | * @flash_node: [BOARDSPECIFIC] device node describing this instance |
addb2e16 | 734 | * @read_byte: [REPLACEABLE] read one byte from the chip |
addb2e16 | 735 | * @read_word: [REPLACEABLE] read one word from the chip |
ff94bc40 HS |
736 | * @write_byte: [REPLACEABLE] write a single byte to the chip on the |
737 | * low 8 I/O lines | |
addb2e16 BS |
738 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
739 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
addb2e16 | 740 | * @select_chip: [REPLACEABLE] select chip nr |
ff94bc40 HS |
741 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
742 | * @block_markbad: [REPLACEABLE] mark a block bad | |
2a8e0fc8 | 743 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
cfa460ad | 744 | * ALE/CLE/nCE. Also used to write command and address |
dfe64e2c | 745 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
2a8e0fc8 CH |
746 | * device ready/busy line. If set to NULL no access to |
747 | * ready/busy is available and the ready/busy information | |
748 | * is read from the chip status register. | |
749 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
750 | * commands to the chip. | |
751 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
752 | * ready. | |
ff94bc40 HS |
753 | * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for |
754 | * setting the read-retry mode. Mostly needed for MLC NAND. | |
dfe64e2c | 755 | * @ecc: [BOARDSPECIFIC] ECC control structure |
cfa460ad | 756 | * @buffers: buffer structure for read/write |
436fb2b8 | 757 | * @buf_align: minimum buffer alignment required by a platform |
cfa460ad | 758 | * @hwcontrol: platform-specific hardware control structure |
d3963721 | 759 | * @erase: [REPLACEABLE] erase function |
addb2e16 | 760 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
2a8e0fc8 CH |
761 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
762 | * data from array to read regs (tR). | |
b9365a26 | 763 | * @state: [INTERN] the current state of the NAND device |
dfe64e2c SL |
764 | * @oob_poi: "poison value buffer," used for laying out OOB data |
765 | * before writing | |
2a8e0fc8 CH |
766 | * @page_shift: [INTERN] number of address bits in a page (column |
767 | * address bits). | |
addb2e16 BS |
768 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
769 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
770 | * @chip_shift: [INTERN] number of address bits in one chip | |
2a8e0fc8 CH |
771 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
772 | * be set to inform nand_scan about special functionality. | |
773 | * See the defines for further explanation. | |
dfe64e2c SL |
774 | * @bbt_options: [INTERN] bad block specific options. All options used |
775 | * here must come from bbm.h. By default, these options | |
776 | * will be copied to the appropriate nand_bbt_descr's. | |
2a8e0fc8 CH |
777 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
778 | * area. | |
dfe64e2c SL |
779 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
780 | * bad block marker position; i.e., BBM == 11110111b is | |
781 | * not bad when badblockbits == 7 | |
ff94bc40 HS |
782 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
783 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. | |
784 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
785 | * to be correctable. If unknown, set to zero. | |
786 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
787 | * also from the datasheet. It is the recommended ECC step | |
788 | * size, if known; if unknown, set to zero. | |
d3963721 | 789 | * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is |
27c4792c BB |
790 | * set to the actually used ONFI mode if the chip is |
791 | * ONFI compliant or deduced from the datasheet if | |
792 | * the NAND chip is not ONFI compliant. | |
addb2e16 BS |
793 | * @numchips: [INTERN] number of physical chips |
794 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
795 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
2a8e0fc8 CH |
796 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
797 | * data_buf. | |
40462e54 PB |
798 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
799 | * currently in data_buf. | |
cfa460ad | 800 | * @subpagesize: [INTERN] holds the subpagesize |
2a8e0fc8 CH |
801 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
802 | * non 0 if ONFI supported. | |
4e67c571 HS |
803 | * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), |
804 | * non 0 if JEDEC supported. | |
2a8e0fc8 CH |
805 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is |
806 | * supported, 0 otherwise. | |
4e67c571 HS |
807 | * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is |
808 | * supported, 0 otherwise. | |
ff94bc40 HS |
809 | * @read_retries: [INTERN] the number of read retry modes supported |
810 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand | |
811 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
52cde35b BB |
812 | * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If |
813 | * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this | |
814 | * means the configuration should not be applied but | |
815 | * only checked. | |
addb2e16 | 816 | * @bbt: [INTERN] bad block table pointer |
2a8e0fc8 CH |
817 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
818 | * lookup. | |
addb2e16 | 819 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
2a8e0fc8 CH |
820 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
821 | * bad block scan. | |
822 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
dfe64e2c | 823 | * structure which is shared among multiple independent |
2a8e0fc8 | 824 | * devices. |
dfe64e2c | 825 | * @priv: [OPTIONAL] pointer to private chip data |
cfa460ad | 826 | * @write_page: [REPLACEABLE] High-level page write function |
addb2e16 | 827 | */ |
dc7c9a1a WD |
828 | |
829 | struct nand_chip { | |
b616d9b0 | 830 | struct mtd_info mtd; |
2a8e0fc8 CH |
831 | void __iomem *IO_ADDR_R; |
832 | void __iomem *IO_ADDR_W; | |
833 | ||
42bd19ce BN |
834 | int flash_node; |
835 | ||
2a8e0fc8 CH |
836 | uint8_t (*read_byte)(struct mtd_info *mtd); |
837 | u16 (*read_word)(struct mtd_info *mtd); | |
ff94bc40 | 838 | void (*write_byte)(struct mtd_info *mtd, uint8_t byte); |
2a8e0fc8 CH |
839 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
840 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
2a8e0fc8 | 841 | void (*select_chip)(struct mtd_info *mtd, int chip); |
ceee07b6 | 842 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs); |
2a8e0fc8 CH |
843 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
844 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
2a8e0fc8 CH |
845 | int (*dev_ready)(struct mtd_info *mtd); |
846 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
847 | int page_addr); | |
848 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
d3963721 | 849 | int (*erase)(struct mtd_info *mtd, int page); |
2a8e0fc8 | 850 | int (*scan_bbt)(struct mtd_info *mtd); |
2a8e0fc8 | 851 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
ff94bc40 | 852 | uint32_t offset, int data_len, const uint8_t *buf, |
4d75596e | 853 | int oob_required, int page, int raw); |
dfe64e2c SL |
854 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
855 | int feature_addr, uint8_t *subfeature_para); | |
856 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
857 | int feature_addr, uint8_t *subfeature_para); | |
ff94bc40 | 858 | int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); |
52cde35b BB |
859 | int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, |
860 | const struct nand_data_interface *conf); | |
27c4792c | 861 | |
2a8e0fc8 CH |
862 | |
863 | int chip_delay; | |
864 | unsigned int options; | |
dfe64e2c | 865 | unsigned int bbt_options; |
2a8e0fc8 CH |
866 | |
867 | int page_shift; | |
868 | int phys_erase_shift; | |
869 | int bbt_erase_shift; | |
870 | int chip_shift; | |
871 | int numchips; | |
872 | uint64_t chipsize; | |
873 | int pagemask; | |
874 | int pagebuf; | |
40462e54 | 875 | unsigned int pagebuf_bitflips; |
2a8e0fc8 | 876 | int subpagesize; |
ff94bc40 HS |
877 | uint8_t bits_per_cell; |
878 | uint16_t ecc_strength_ds; | |
879 | uint16_t ecc_step_ds; | |
d3963721 | 880 | int onfi_timing_mode_default; |
2a8e0fc8 CH |
881 | int badblockpos; |
882 | int badblockbits; | |
883 | ||
884 | int onfi_version; | |
4e67c571 | 885 | int jedec_version; |
ff94bc40 | 886 | struct nand_onfi_params onfi_params; |
4e67c571 HS |
887 | struct nand_jedec_params jedec_params; |
888 | ||
27c4792c BB |
889 | struct nand_data_interface *data_interface; |
890 | ||
ff94bc40 HS |
891 | int read_retries; |
892 | ||
893 | flstate_t state; | |
cfa460ad | 894 | |
2a8e0fc8 CH |
895 | uint8_t *oob_poi; |
896 | struct nand_hw_control *controller; | |
897 | struct nand_ecclayout *ecclayout; | |
cfa460ad WJ |
898 | |
899 | struct nand_ecc_ctrl ecc; | |
900 | struct nand_buffers *buffers; | |
436fb2b8 | 901 | unsigned long buf_align; |
cfa460ad WJ |
902 | struct nand_hw_control hwcontrol; |
903 | ||
2a8e0fc8 CH |
904 | uint8_t *bbt; |
905 | struct nand_bbt_descr *bbt_td; | |
906 | struct nand_bbt_descr *bbt_md; | |
cfa460ad | 907 | |
2a8e0fc8 | 908 | struct nand_bbt_descr *badblock_pattern; |
cfa460ad | 909 | |
2a8e0fc8 | 910 | void *priv; |
dc7c9a1a WD |
911 | }; |
912 | ||
17cb4b8f SW |
913 | static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) |
914 | { | |
915 | return container_of(mtd, struct nand_chip, mtd); | |
916 | } | |
917 | ||
918 | static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) | |
919 | { | |
920 | return &chip->mtd; | |
921 | } | |
922 | ||
923 | static inline void *nand_get_controller_data(struct nand_chip *chip) | |
924 | { | |
925 | return chip->priv; | |
926 | } | |
927 | ||
928 | static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) | |
929 | { | |
930 | chip->priv = priv; | |
931 | } | |
932 | ||
e2211743 WD |
933 | /* |
934 | * NAND Flash Manufacturer ID Codes | |
935 | */ | |
936 | #define NAND_MFR_TOSHIBA 0x98 | |
937 | #define NAND_MFR_SAMSUNG 0xec | |
addb2e16 BS |
938 | #define NAND_MFR_FUJITSU 0x04 |
939 | #define NAND_MFR_NATIONAL 0x8f | |
940 | #define NAND_MFR_RENESAS 0x07 | |
941 | #define NAND_MFR_STMICRO 0x20 | |
cfa460ad | 942 | #define NAND_MFR_HYNIX 0xad |
7ebb4479 | 943 | #define NAND_MFR_MICRON 0x2c |
c45912d8 | 944 | #define NAND_MFR_AMD 0x01 |
dfe64e2c SL |
945 | #define NAND_MFR_MACRONIX 0xc2 |
946 | #define NAND_MFR_EON 0x92 | |
ff94bc40 HS |
947 | #define NAND_MFR_SANDISK 0x45 |
948 | #define NAND_MFR_INTEL 0x89 | |
d3963721 | 949 | #define NAND_MFR_ATO 0x9b |
ff94bc40 HS |
950 | |
951 | /* The maximum expected count of bytes in the NAND ID sequence */ | |
952 | #define NAND_MAX_ID_LEN 8 | |
953 | ||
954 | /* | |
955 | * A helper for defining older NAND chips where the second ID byte fully | |
956 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
957 | * size). All these chips have 512 bytes NAND page size. | |
958 | */ | |
959 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ | |
960 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
961 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
962 | ||
963 | /* | |
964 | * A helper for defining newer chips which report their page size and | |
965 | * eraseblock size via the extended ID bytes. | |
966 | * | |
967 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
968 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
969 | * device ID now only represented a particular total chip size (and voltage, | |
970 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
971 | * using the same device ID. | |
972 | */ | |
973 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ | |
974 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
975 | .options = (opts) } | |
976 | ||
977 | #define NAND_ECC_INFO(_strength, _step) \ | |
978 | { .strength_ds = (_strength), .step_ds = (_step) } | |
979 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
980 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
e2211743 | 981 | |
addb2e16 BS |
982 | /** |
983 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
ff94bc40 HS |
984 | * @name: a human-readable name of the NAND chip |
985 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
986 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same | |
987 | * memory address as @id[0]) | |
988 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
989 | * address as @id[1]) | |
990 | * @id: full device ID array | |
991 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as | |
992 | * well as the eraseblock size) is determined from the extended NAND | |
993 | * chip ID array) | |
994 | * @chipsize: total chip size in MiB | |
995 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) | |
996 | * @options: stores various chip bit options | |
997 | * @id_len: The valid length of the @id. | |
998 | * @oobsize: OOB size | |
d3963721 | 999 | * @ecc: ECC correctability and step information from the datasheet. |
ff94bc40 HS |
1000 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
1001 | * @ecc_strength_ds in nand_chip{}. | |
1002 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
1003 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
1004 | * For example, the "4bit ECC for each 512Byte" can be set with | |
1005 | * NAND_ECC_INFO(4, 512). | |
d3963721 SW |
1006 | * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND |
1007 | * reset. Should be deduced from timings described | |
1008 | * in the datasheet. | |
1009 | * | |
e2211743 WD |
1010 | */ |
1011 | struct nand_flash_dev { | |
addb2e16 | 1012 | char *name; |
ff94bc40 HS |
1013 | union { |
1014 | struct { | |
1015 | uint8_t mfr_id; | |
1016 | uint8_t dev_id; | |
1017 | }; | |
1018 | uint8_t id[NAND_MAX_ID_LEN]; | |
1019 | }; | |
1020 | unsigned int pagesize; | |
1021 | unsigned int chipsize; | |
1022 | unsigned int erasesize; | |
1023 | unsigned int options; | |
1024 | uint16_t id_len; | |
1025 | uint16_t oobsize; | |
1026 | struct { | |
1027 | uint16_t strength_ds; | |
1028 | uint16_t step_ds; | |
1029 | } ecc; | |
d3963721 | 1030 | int onfi_timing_mode_default; |
e2211743 WD |
1031 | }; |
1032 | ||
addb2e16 BS |
1033 | /** |
1034 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
1035 | * @name: Manufacturer name | |
b9365a26 | 1036 | * @id: manufacturer ID code of device. |
addb2e16 BS |
1037 | */ |
1038 | struct nand_manufacturers { | |
1039 | int id; | |
2a8e0fc8 | 1040 | char *name; |
addb2e16 BS |
1041 | }; |
1042 | ||
ff94bc40 HS |
1043 | extern struct nand_flash_dev nand_flash_ids[]; |
1044 | extern struct nand_manufacturers nand_manuf_ids[]; | |
addb2e16 | 1045 | |
6a1ff76e SH |
1046 | int nand_default_bbt(struct mtd_info *mtd); |
1047 | int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); | |
1048 | int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); | |
1049 | int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
1050 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
cfa460ad | 1051 | int allowbbt); |
6a1ff76e | 1052 | int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, |
2a8e0fc8 | 1053 | size_t *retlen, uint8_t *buf); |
addb2e16 | 1054 | |
dc7c9a1a WD |
1055 | /* |
1056 | * Constants for oob configuration | |
1057 | */ | |
addb2e16 BS |
1058 | #define NAND_SMALL_BADBLOCK_POS 5 |
1059 | #define NAND_LARGE_BADBLOCK_POS 0 | |
1060 | ||
cfa460ad WJ |
1061 | /** |
1062 | * struct platform_nand_chip - chip level device structure | |
1063 | * @nr_chips: max. number of chips to scan for | |
1064 | * @chip_offset: chip number offset | |
1065 | * @nr_partitions: number of partitions pointed to by partitions (or zero) | |
1066 | * @partitions: mtd partition list | |
1067 | * @chip_delay: R/B delay value in us | |
1068 | * @options: Option flags, e.g. 16bit buswidth | |
dfe64e2c | 1069 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
cfa460ad | 1070 | * @part_probe_types: NULL-terminated array of probe types |
cfa460ad WJ |
1071 | */ |
1072 | struct platform_nand_chip { | |
2a8e0fc8 CH |
1073 | int nr_chips; |
1074 | int chip_offset; | |
1075 | int nr_partitions; | |
1076 | struct mtd_partition *partitions; | |
2a8e0fc8 CH |
1077 | int chip_delay; |
1078 | unsigned int options; | |
dfe64e2c | 1079 | unsigned int bbt_options; |
2a8e0fc8 | 1080 | const char **part_probe_types; |
cfa460ad WJ |
1081 | }; |
1082 | ||
2a8e0fc8 CH |
1083 | /* Keep gcc happy */ |
1084 | struct platform_device; | |
1085 | ||
cfa460ad WJ |
1086 | /** |
1087 | * struct platform_nand_ctrl - controller level device structure | |
ff94bc40 HS |
1088 | * @probe: platform specific function to probe/setup hardware |
1089 | * @remove: platform specific function to remove/teardown hardware | |
cfa460ad WJ |
1090 | * @hwcontrol: platform specific hardware control structure |
1091 | * @dev_ready: platform specific function to read ready/busy pin | |
1092 | * @select_chip: platform specific chip select function | |
1093 | * @cmd_ctrl: platform specific function for controlling | |
1094 | * ALE/CLE/nCE. Also used to write command and address | |
ff94bc40 HS |
1095 | * @write_buf: platform specific function for write buffer |
1096 | * @read_buf: platform specific function for read buffer | |
1097 | * @read_byte: platform specific function to read one byte from chip | |
cfa460ad WJ |
1098 | * @priv: private data to transport driver specific settings |
1099 | * | |
1100 | * All fields are optional and depend on the hardware driver requirements | |
1101 | */ | |
1102 | struct platform_nand_ctrl { | |
ff94bc40 HS |
1103 | int (*probe)(struct platform_device *pdev); |
1104 | void (*remove)(struct platform_device *pdev); | |
2a8e0fc8 CH |
1105 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
1106 | int (*dev_ready)(struct mtd_info *mtd); | |
1107 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
1108 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
ff94bc40 HS |
1109 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
1110 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
dfe64e2c | 1111 | unsigned char (*read_byte)(struct mtd_info *mtd); |
2a8e0fc8 | 1112 | void *priv; |
cfa460ad WJ |
1113 | }; |
1114 | ||
1115 | /** | |
1116 | * struct platform_nand_data - container structure for platform-specific data | |
1117 | * @chip: chip level chip structure | |
1118 | * @ctrl: controller level device structure | |
1119 | */ | |
1120 | struct platform_nand_data { | |
2a8e0fc8 CH |
1121 | struct platform_nand_chip chip; |
1122 | struct platform_nand_ctrl ctrl; | |
cfa460ad WJ |
1123 | }; |
1124 | ||
ff94bc40 HS |
1125 | #ifdef CONFIG_SYS_NAND_ONFI_DETECTION |
1126 | /* return the supported features. */ | |
1127 | static inline int onfi_feature(struct nand_chip *chip) | |
1128 | { | |
1129 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
1130 | } | |
82645f81 | 1131 | |
dfe64e2c | 1132 | /* return the supported asynchronous timing mode. */ |
dfe64e2c SL |
1133 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) |
1134 | { | |
1135 | if (!chip->onfi_version) | |
1136 | return ONFI_TIMING_MODE_UNKNOWN; | |
1137 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
1138 | } | |
1139 | ||
1140 | /* return the supported synchronous timing mode. */ | |
1141 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
1142 | { | |
1143 | if (!chip->onfi_version) | |
1144 | return ONFI_TIMING_MODE_UNKNOWN; | |
1145 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
1146 | } | |
4c61f79b MY |
1147 | #else |
1148 | static inline int onfi_feature(struct nand_chip *chip) | |
1149 | { | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
1154 | { | |
1155 | return ONFI_TIMING_MODE_UNKNOWN; | |
1156 | } | |
1157 | ||
1158 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
1159 | { | |
1160 | return ONFI_TIMING_MODE_UNKNOWN; | |
1161 | } | |
dfe64e2c SL |
1162 | #endif |
1163 | ||
46deff57 SH |
1164 | int onfi_init_data_interface(struct nand_chip *chip, |
1165 | struct nand_data_interface *iface, | |
1166 | enum nand_data_interface_type type, | |
1167 | int timing_mode); | |
1168 | ||
ff94bc40 HS |
1169 | /* |
1170 | * Check if it is a SLC nand. | |
1171 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
1172 | * We do not distinguish the MLC and TLC now. | |
1173 | */ | |
1174 | static inline bool nand_is_slc(struct nand_chip *chip) | |
1175 | { | |
1176 | return chip->bits_per_cell == 1; | |
1177 | } | |
1178 | ||
27ce9e42 BN |
1179 | /** |
1180 | * Check if the opcode's address should be sent only on the lower 8 bits | |
1181 | * @command: opcode to check | |
1182 | */ | |
1183 | static inline int nand_opcode_8bits(unsigned int command) | |
1184 | { | |
6e1899e6 DM |
1185 | switch (command) { |
1186 | case NAND_CMD_READID: | |
1187 | case NAND_CMD_PARAM: | |
1188 | case NAND_CMD_GET_FEATURES: | |
1189 | case NAND_CMD_SET_FEATURES: | |
1190 | return 1; | |
1191 | default: | |
1192 | break; | |
1193 | } | |
1194 | return 0; | |
27ce9e42 BN |
1195 | } |
1196 | ||
4e67c571 HS |
1197 | /* return the supported JEDEC features. */ |
1198 | static inline int jedec_feature(struct nand_chip *chip) | |
1199 | { | |
1200 | return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) | |
1201 | : 0; | |
1202 | } | |
1203 | ||
ff94bc40 HS |
1204 | /* Standard NAND functions from nand_base.c */ |
1205 | void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1206 | void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1207 | void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); | |
1208 | void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); | |
1209 | uint8_t nand_read_byte(struct mtd_info *mtd); | |
d3963721 | 1210 | |
d3963721 SW |
1211 | /* get timing characteristics from ONFI timing mode. */ |
1212 | const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); | |
b893e833 SH |
1213 | /* get data interface from ONFI timing mode 0, used after reset. */ |
1214 | const struct nand_data_interface *nand_get_default_data_interface(void); | |
ceee07b6 SW |
1215 | |
1216 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1217 | void *ecc, int ecclen, | |
1218 | void *extraoob, int extraooblen, | |
1219 | int threshold); | |
1728eb57 SH |
1220 | |
1221 | /* Reset and initialize a NAND device */ | |
3d841b32 | 1222 | int nand_reset(struct nand_chip *chip, int chipnr); |
1728eb57 | 1223 | |
e2211743 | 1224 | #endif /* __LINUX_MTD_NAND_H */ |