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Commit | Line | Data |
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71f95118 | 1 | /* |
4a6ee172 | 2 | * Copyright 2008,2010 Freescale Semiconductor, Inc |
272cc70b AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based (loosely) on the Linux code | |
71f95118 | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
71f95118 WD |
8 | */ |
9 | ||
10 | #ifndef _MMC_H_ | |
11 | #define _MMC_H_ | |
71f95118 | 12 | |
272cc70b | 13 | #include <linux/list.h> |
0d986e61 | 14 | #include <linux/compiler.h> |
272cc70b AF |
15 | |
16 | #define SD_VERSION_SD 0x20000 | |
1741c64d | 17 | #define SD_VERSION_3 (SD_VERSION_SD | 0x300) |
64f4a619 JC |
18 | #define SD_VERSION_2 (SD_VERSION_SD | 0x200) |
19 | #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) | |
20 | #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) | |
272cc70b AF |
21 | #define MMC_VERSION_MMC 0x10000 |
22 | #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) | |
64f4a619 JC |
23 | #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) |
24 | #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) | |
25 | #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) | |
26 | #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) | |
27 | #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) | |
28 | #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) | |
29 | #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) | |
30 | #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) | |
31 | #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) | |
32 | #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) | |
272cc70b AF |
33 | |
34 | #define MMC_MODE_HS 0x001 | |
35 | #define MMC_MODE_HS_52MHz 0x010 | |
36 | #define MMC_MODE_4BIT 0x100 | |
37 | #define MMC_MODE_8BIT 0x200 | |
d52ebf10 | 38 | #define MMC_MODE_SPI 0x400 |
b1f1e821 | 39 | #define MMC_MODE_HC 0x800 |
272cc70b | 40 | |
62722036 ŁM |
41 | #define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT) |
42 | #define MMC_MODE_WIDTH_BITS_SHIFT 8 | |
43 | ||
272cc70b AF |
44 | #define SD_DATA_4BIT 0x00040000 |
45 | ||
79b91de9 | 46 | #define IS_SD(x) (x->version & SD_VERSION_SD) |
272cc70b AF |
47 | |
48 | #define MMC_DATA_READ 1 | |
49 | #define MMC_DATA_WRITE 2 | |
50 | ||
51 | #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ | |
52 | #define UNUSABLE_ERR -17 /* Unusable Card */ | |
53 | #define COMM_ERR -18 /* Communications Error */ | |
54 | #define TIMEOUT -19 | |
e9550449 | 55 | #define IN_PROGRESS -20 /* operation is in progress */ |
272cc70b | 56 | |
341188b9 HS |
57 | #define MMC_CMD_GO_IDLE_STATE 0 |
58 | #define MMC_CMD_SEND_OP_COND 1 | |
59 | #define MMC_CMD_ALL_SEND_CID 2 | |
60 | #define MMC_CMD_SET_RELATIVE_ADDR 3 | |
61 | #define MMC_CMD_SET_DSR 4 | |
272cc70b | 62 | #define MMC_CMD_SWITCH 6 |
341188b9 | 63 | #define MMC_CMD_SELECT_CARD 7 |
272cc70b | 64 | #define MMC_CMD_SEND_EXT_CSD 8 |
341188b9 HS |
65 | #define MMC_CMD_SEND_CSD 9 |
66 | #define MMC_CMD_SEND_CID 10 | |
272cc70b | 67 | #define MMC_CMD_STOP_TRANSMISSION 12 |
341188b9 HS |
68 | #define MMC_CMD_SEND_STATUS 13 |
69 | #define MMC_CMD_SET_BLOCKLEN 16 | |
70 | #define MMC_CMD_READ_SINGLE_BLOCK 17 | |
71 | #define MMC_CMD_READ_MULTIPLE_BLOCK 18 | |
272cc70b AF |
72 | #define MMC_CMD_WRITE_SINGLE_BLOCK 24 |
73 | #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 | |
e6f99a56 LW |
74 | #define MMC_CMD_ERASE_GROUP_START 35 |
75 | #define MMC_CMD_ERASE_GROUP_END 36 | |
76 | #define MMC_CMD_ERASE 38 | |
341188b9 | 77 | #define MMC_CMD_APP_CMD 55 |
d52ebf10 TC |
78 | #define MMC_CMD_SPI_READ_OCR 58 |
79 | #define MMC_CMD_SPI_CRC_ON_OFF 59 | |
3690d6d6 A |
80 | #define MMC_CMD_RES_MAN 62 |
81 | ||
82 | #define MMC_CMD62_ARG1 0xefac62ec | |
83 | #define MMC_CMD62_ARG2 0xcbaea7 | |
84 | ||
341188b9 | 85 | |
341188b9 | 86 | #define SD_CMD_SEND_RELATIVE_ADDR 3 |
272cc70b | 87 | #define SD_CMD_SWITCH_FUNC 6 |
341188b9 HS |
88 | #define SD_CMD_SEND_IF_COND 8 |
89 | ||
90 | #define SD_CMD_APP_SET_BUS_WIDTH 6 | |
e6f99a56 LW |
91 | #define SD_CMD_ERASE_WR_BLK_START 32 |
92 | #define SD_CMD_ERASE_WR_BLK_END 33 | |
341188b9 | 93 | #define SD_CMD_APP_SEND_OP_COND 41 |
272cc70b AF |
94 | #define SD_CMD_APP_SEND_SCR 51 |
95 | ||
96 | /* SCR definitions in different words */ | |
97 | #define SD_HIGHSPEED_BUSY 0x00020000 | |
98 | #define SD_HIGHSPEED_SUPPORTED 0x00020000 | |
99 | ||
100 | #define MMC_HS_TIMING 0x00000100 | |
101 | #define MMC_HS_52MHZ 0x2 | |
102 | ||
abe2c93f TC |
103 | #define OCR_BUSY 0x80000000 |
104 | #define OCR_HCS 0x40000000 | |
31cacbab RR |
105 | #define OCR_VOLTAGE_MASK 0x007FFF80 |
106 | #define OCR_ACCESS_MODE 0x60000000 | |
272cc70b | 107 | |
e6f99a56 LW |
108 | #define SECURE_ERASE 0x80000000 |
109 | ||
5d4fc8d9 | 110 | #define MMC_STATUS_MASK (~0x0206BF7F) |
abe2c93f TC |
111 | #define MMC_STATUS_RDY_FOR_DATA (1 << 8) |
112 | #define MMC_STATUS_CURR_STATE (0xf << 9) | |
ed018b21 | 113 | #define MMC_STATUS_ERROR (1 << 19) |
5d4fc8d9 | 114 | |
d617c426 JK |
115 | #define MMC_STATE_PRG (7 << 9) |
116 | ||
272cc70b AF |
117 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
118 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ | |
119 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
120 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
121 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
122 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
123 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
124 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
125 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
126 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
127 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
128 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
129 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
130 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
131 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
132 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
133 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
134 | ||
135 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ | |
136 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte | |
137 | addressed by index which are | |
138 | 1 in value field */ | |
139 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte | |
140 | addressed by index, which are | |
141 | 1 in value field */ | |
142 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ | |
143 | ||
144 | #define SD_SWITCH_CHECK 0 | |
145 | #define SD_SWITCH_SWITCH 1 | |
146 | ||
147 | /* | |
148 | * EXT_CSD fields | |
149 | */ | |
f866a46d | 150 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ |
0560db18 | 151 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ |
f866a46d | 152 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
0560db18 | 153 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
3690d6d6 | 154 | #define EXT_CSD_BOOT_BUS_WIDTH 177 |
0560db18 LW |
155 | #define EXT_CSD_PART_CONF 179 /* R/W */ |
156 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ | |
157 | #define EXT_CSD_HS_TIMING 185 /* R/W */ | |
158 | #define EXT_CSD_REV 192 /* RO */ | |
159 | #define EXT_CSD_CARD_TYPE 196 /* RO */ | |
160 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ | |
f866a46d | 161 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
0560db18 | 162 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ |
8948ea83 | 163 | #define EXT_CSD_BOOT_MULT 226 /* RO */ |
272cc70b AF |
164 | |
165 | /* | |
166 | * EXT_CSD field definitions | |
167 | */ | |
168 | ||
abe2c93f TC |
169 | #define EXT_CSD_CMD_SET_NORMAL (1 << 0) |
170 | #define EXT_CSD_CMD_SET_SECURE (1 << 1) | |
171 | #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) | |
272cc70b | 172 | |
abe2c93f TC |
173 | #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ |
174 | #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ | |
272cc70b AF |
175 | |
176 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ | |
177 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | |
178 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ | |
341188b9 | 179 | |
3690d6d6 A |
180 | #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) |
181 | #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) | |
182 | #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) | |
183 | #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) | |
184 | ||
185 | #define EXT_CSD_BOOT_ACK(x) (x << 6) | |
186 | #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) | |
187 | #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) | |
188 | ||
189 | ||
1de97f98 AF |
190 | #define R1_ILLEGAL_COMMAND (1 << 22) |
191 | #define R1_APP_CMD (1 << 5) | |
192 | ||
272cc70b | 193 | #define MMC_RSP_PRESENT (1 << 0) |
abe2c93f TC |
194 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
195 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ | |
196 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ | |
197 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ | |
272cc70b | 198 | |
abe2c93f TC |
199 | #define MMC_RSP_NONE (0) |
200 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b AF |
201 | #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ |
202 | MMC_RSP_BUSY) | |
abe2c93f TC |
203 | #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) |
204 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) | |
205 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) | |
206 | #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
207 | #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
208 | #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b | 209 | |
bc897b1d LW |
210 | #define MMCPART_NOAVAILABLE (0xff) |
211 | #define PART_ACCESS_MASK (0x7) | |
212 | #define PART_SUPPORT (0x1) | |
71f95118 | 213 | |
8bfa195e SG |
214 | /* Maximum block size for MMC */ |
215 | #define MMC_MAX_BLOCK_LEN 512 | |
216 | ||
3690d6d6 A |
217 | /* The number of MMC physical partitions. These consist of: |
218 | * boot partitions (2), general purpose partitions (4) in MMC v4.4. | |
219 | */ | |
220 | #define MMC_NUM_BOOT_PARTITION 2 | |
221 | ||
1de97f98 AF |
222 | struct mmc_cid { |
223 | unsigned long psn; | |
224 | unsigned short oid; | |
225 | unsigned char mid; | |
226 | unsigned char prv; | |
227 | unsigned char mdt; | |
228 | char pnm[7]; | |
229 | }; | |
230 | ||
272cc70b AF |
231 | struct mmc_cmd { |
232 | ushort cmdidx; | |
233 | uint resp_type; | |
234 | uint cmdarg; | |
0b453ffe | 235 | uint response[4]; |
272cc70b AF |
236 | }; |
237 | ||
238 | struct mmc_data { | |
239 | union { | |
240 | char *dest; | |
241 | const char *src; /* src buffers don't get written to */ | |
242 | }; | |
243 | uint flags; | |
244 | uint blocks; | |
245 | uint blocksize; | |
246 | }; | |
247 | ||
248 | struct mmc { | |
249 | struct list_head link; | |
250 | char name[32]; | |
251 | void *priv; | |
252 | uint voltages; | |
253 | uint version; | |
bc897b1d | 254 | uint has_init; |
272cc70b AF |
255 | uint f_min; |
256 | uint f_max; | |
257 | int high_capacity; | |
258 | uint bus_width; | |
259 | uint clock; | |
260 | uint card_caps; | |
261 | uint host_caps; | |
262 | uint ocr; | |
263 | uint scr[2]; | |
264 | uint csd[4]; | |
0b453ffe | 265 | uint cid[4]; |
272cc70b | 266 | ushort rca; |
bc897b1d LW |
267 | char part_config; |
268 | char part_num; | |
272cc70b AF |
269 | uint tran_speed; |
270 | uint read_bl_len; | |
271 | uint write_bl_len; | |
e6f99a56 | 272 | uint erase_grp_size; |
272cc70b | 273 | u64 capacity; |
f866a46d SW |
274 | u64 capacity_user; |
275 | u64 capacity_boot; | |
276 | u64 capacity_rpmb; | |
277 | u64 capacity_gp[4]; | |
272cc70b AF |
278 | block_dev_desc_t block_dev; |
279 | int (*send_cmd)(struct mmc *mmc, | |
280 | struct mmc_cmd *cmd, struct mmc_data *data); | |
281 | void (*set_ios)(struct mmc *mmc); | |
282 | int (*init)(struct mmc *mmc); | |
48972d90 | 283 | int (*getcd)(struct mmc *mmc); |
d23d8d7e | 284 | int (*getwp)(struct mmc *mmc); |
57418d21 | 285 | uint b_max; |
e9550449 CLC |
286 | char op_cond_pending; /* 1 if we are waiting on an op_cond command */ |
287 | char init_in_progress; /* 1 if we have done mmc_start_init() */ | |
288 | char preinit; /* start init as early as possible */ | |
289 | uint op_cond_response; /* the response byte from the last op_cond */ | |
272cc70b AF |
290 | }; |
291 | ||
292 | int mmc_register(struct mmc *mmc); | |
293 | int mmc_initialize(bd_t *bis); | |
294 | int mmc_init(struct mmc *mmc); | |
295 | int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); | |
4a6ee172 | 296 | void mmc_set_clock(struct mmc *mmc, uint clock); |
272cc70b | 297 | struct mmc *find_mmc_device(int dev_num); |
89716964 | 298 | int mmc_set_dev(int dev_num); |
272cc70b | 299 | void print_mmc_devices(char separator); |
ea6ebe21 | 300 | int get_mmc_num(void); |
314284b1 | 301 | int board_mmc_getcd(struct mmc *mmc); |
bc897b1d | 302 | int mmc_switch_part(int dev_num, unsigned int part_num); |
48972d90 | 303 | int mmc_getcd(struct mmc *mmc); |
d23d8d7e | 304 | int mmc_getwp(struct mmc *mmc); |
0d986e61 | 305 | void spl_mmc_load(void) __noreturn; |
3690d6d6 A |
306 | /* Function to change the size of boot partition and rpmb partitions */ |
307 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
308 | unsigned long rpmbsize); | |
309 | /* Function to send commands to open/close the specified boot partition */ | |
310 | int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); | |
272cc70b | 311 | |
e9550449 CLC |
312 | /** |
313 | * Start device initialization and return immediately; it does not block on | |
314 | * polling OCR (operation condition register) status. Then you should call | |
315 | * mmc_init, which would block on polling OCR status and complete the device | |
316 | * initializatin. | |
317 | * | |
318 | * @param mmc Pointer to a MMC device struct | |
319 | * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. | |
320 | */ | |
321 | int mmc_start_init(struct mmc *mmc); | |
322 | ||
323 | /** | |
324 | * Set preinit flag of mmc device. | |
325 | * | |
326 | * This will cause the device to be pre-inited during mmc_initialize(), | |
327 | * which may save boot time if the device is not accessed until later. | |
328 | * Some eMMC devices take 200-300ms to init, but unfortunately they | |
329 | * must be sent a series of commands to even get them to start preparing | |
330 | * for operation. | |
331 | * | |
332 | * @param mmc Pointer to a MMC device struct | |
333 | * @param preinit preinit flag value | |
334 | */ | |
335 | void mmc_set_preinit(struct mmc *mmc, int preinit); | |
336 | ||
1592ef85 | 337 | #ifdef CONFIG_GENERIC_MMC |
d52ebf10 TC |
338 | #define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) |
339 | struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); | |
1592ef85 | 340 | #else |
272cc70b AF |
341 | int mmc_legacy_init(int verbose); |
342 | #endif | |
1592ef85 | 343 | |
71f95118 | 344 | #endif /* _MMC_H_ */ |