[people/ms/u-boot.git] / include / mmc.h

/*
 * Copyright 2008,2010 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based (loosely) on the Linux code
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _MMC_H_
#define _MMC_H_

#include <linux/list.h>
#include <linux/compiler.h>
#include <part.h>

#define SD_VERSION_SD	0x20000
#define SD_VERSION_3	(SD_VERSION_SD | 0x300)
#define SD_VERSION_2	(SD_VERSION_SD | 0x200)
#define SD_VERSION_1_0	(SD_VERSION_SD | 0x100)
#define SD_VERSION_1_10	(SD_VERSION_SD | 0x10a)
#define MMC_VERSION_MMC		0x10000
#define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x102)
#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x104)
#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x202)
#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x300)
#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x400)
#define MMC_VERSION_4_1		(MMC_VERSION_MMC | 0x401)
#define MMC_VERSION_4_2		(MMC_VERSION_MMC | 0x402)
#define MMC_VERSION_4_3		(MMC_VERSION_MMC | 0x403)
#define MMC_VERSION_4_41	(MMC_VERSION_MMC | 0x429)
#define MMC_VERSION_4_5		(MMC_VERSION_MMC | 0x405)
#define MMC_VERSION_5_0		(MMC_VERSION_MMC | 0x500)

#define MMC_MODE_HS		(1 << 0)
#define MMC_MODE_HS_52MHz	(1 << 1)
#define MMC_MODE_4BIT		(1 << 2)
#define MMC_MODE_8BIT		(1 << 3)
#define MMC_MODE_SPI		(1 << 4)
#define MMC_MODE_HC		(1 << 5)
#define MMC_MODE_DDR_52MHz	(1 << 6)

#define SD_DATA_4BIT	0x00040000

#define IS_SD(x) (x->version & SD_VERSION_SD)

#define MMC_DATA_READ		1
#define MMC_DATA_WRITE		2

#define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
#define UNUSABLE_ERR		-17 /* Unusable Card */
#define COMM_ERR		-18 /* Communications Error */
#define TIMEOUT			-19
#define IN_PROGRESS		-20 /* operation is in progress */
#define SWITCH_ERR		-21 /* Card reports failure to switch mode */

#define MMC_CMD_GO_IDLE_STATE		0
#define MMC_CMD_SEND_OP_COND		1
#define MMC_CMD_ALL_SEND_CID		2
#define MMC_CMD_SET_RELATIVE_ADDR	3
#define MMC_CMD_SET_DSR			4
#define MMC_CMD_SWITCH			6
#define MMC_CMD_SELECT_CARD		7
#define MMC_CMD_SEND_EXT_CSD		8
#define MMC_CMD_SEND_CSD		9
#define MMC_CMD_SEND_CID		10
#define MMC_CMD_STOP_TRANSMISSION	12
#define MMC_CMD_SEND_STATUS		13
#define MMC_CMD_SET_BLOCKLEN		16
#define MMC_CMD_READ_SINGLE_BLOCK	17
#define MMC_CMD_READ_MULTIPLE_BLOCK	18
#define MMC_CMD_SET_BLOCK_COUNT         23
#define MMC_CMD_WRITE_SINGLE_BLOCK	24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
#define MMC_CMD_ERASE_GROUP_START	35
#define MMC_CMD_ERASE_GROUP_END		36
#define MMC_CMD_ERASE			38
#define MMC_CMD_APP_CMD			55
#define MMC_CMD_SPI_READ_OCR		58
#define MMC_CMD_SPI_CRC_ON_OFF		59
#define MMC_CMD_RES_MAN			62

#define MMC_CMD62_ARG1			0xefac62ec
#define MMC_CMD62_ARG2			0xcbaea7


#define SD_CMD_SEND_RELATIVE_ADDR	3
#define SD_CMD_SWITCH_FUNC		6
#define SD_CMD_SEND_IF_COND		8

#define SD_CMD_APP_SET_BUS_WIDTH	6
#define SD_CMD_ERASE_WR_BLK_START	32
#define SD_CMD_ERASE_WR_BLK_END		33
#define SD_CMD_APP_SEND_OP_COND		41
#define SD_CMD_APP_SEND_SCR		51

/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY	0x00020000
#define SD_HIGHSPEED_SUPPORTED	0x00020000

#define OCR_BUSY		0x80000000
#define OCR_HCS			0x40000000
#define OCR_VOLTAGE_MASK	0x007FFF80
#define OCR_ACCESS_MODE		0x60000000

#define SECURE_ERASE		0x80000000

#define MMC_STATUS_MASK		(~0x0206BF7F)
#define MMC_STATUS_SWITCH_ERROR	(1 << 7)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE	(0xf << 9)
#define MMC_STATUS_ERROR	(1 << 19)

#define MMC_STATE_PRG		(7 << 9)

#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */

#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
						addressed by index which are
						1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
						addressed by index, which are
						1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */

#define SD_SWITCH_CHECK		0
#define SD_SWITCH_SWITCH	1

/*
 * EXT_CSD fields
 */
#define EXT_CSD_ENH_START_ADDR		136	/* R/W */
#define EXT_CSD_ENH_SIZE_MULT		140	/* R/W */
#define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
#define EXT_CSD_PARTITION_SETTING	155	/* R/W */
#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
#define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
#define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
#define EXT_CSD_RPMB_MULT		168	/* RO */
#define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
#define EXT_CSD_BOOT_BUS_WIDTH		177
#define EXT_CSD_PART_CONF		179	/* R/W */
#define EXT_CSD_BUS_WIDTH		183	/* R/W */
#define EXT_CSD_HS_TIMING		185	/* R/W */
#define EXT_CSD_REV			192	/* RO */
#define EXT_CSD_CARD_TYPE		196	/* RO */
#define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
#define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
#define EXT_CSD_BOOT_MULT		226	/* RO */

/*
 * EXT_CSD field definitions
 */

#define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
#define EXT_CSD_CMD_SET_SECURE		(1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)

#define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1 << 2)
#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1 << 3)
#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V \
					| EXT_CSD_CARD_TYPE_DDR_1_2V)

#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */

#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)

#define EXT_CSD_BOOT_ACK(x)		(x << 6)
#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)

#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)

#define EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)

#define EXT_CSD_ENH_USR		(1 << 0)	/* user data area is enhanced */
#define EXT_CSD_ENH_GP(x)	(1 << ((x)+1))	/* GP part (x+1) is enhanced */

#define R1_ILLEGAL_COMMAND		(1 << 22)
#define R1_APP_CMD			(1 << 5)

#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */

#define MMC_RSP_NONE	(0)
#define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
			MMC_RSP_BUSY)
#define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3	(MMC_RSP_PRESENT)
#define MMC_RSP_R4	(MMC_RSP_PRESENT)
#define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)

#define MMCPART_NOAVAILABLE	(0xff)
#define PART_ACCESS_MASK	(0x7)
#define PART_SUPPORT		(0x1)
#define ENHNCD_SUPPORT		(0x2)
#define PART_ENH_ATTRIB		(0x1f)

/* Maximum block size for MMC */
#define MMC_MAX_BLOCK_LEN	512

/* The number of MMC physical partitions.  These consist of:
 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 */
#define MMC_NUM_BOOT_PARTITION	2
#define MMC_PART_RPMB           3       /* RPMB partition number */

struct mmc_cid {
	unsigned long psn;
	unsigned short oid;
	unsigned char mid;
	unsigned char prv;
	unsigned char mdt;
	char pnm[7];
};

struct mmc_cmd {
	ushort cmdidx;
	uint resp_type;
	uint cmdarg;
	uint response[4];
};

struct mmc_data {
	union {
		char *dest;
		const char *src; /* src buffers don't get written to */
	};
	uint flags;
	uint blocks;
	uint blocksize;
};

/* forward decl. */
struct mmc;

struct mmc_ops {
	int (*send_cmd)(struct mmc *mmc,
			struct mmc_cmd *cmd, struct mmc_data *data);
	void (*set_ios)(struct mmc *mmc);
	int (*init)(struct mmc *mmc);
	int (*getcd)(struct mmc *mmc);
	int (*getwp)(struct mmc *mmc);
};

struct mmc_config {
	const char *name;
	const struct mmc_ops *ops;
	uint host_caps;
	uint voltages;
	uint f_min;
	uint f_max;
	uint b_max;
	unsigned char part_type;
};

/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
struct mmc {
	struct list_head link;
	const struct mmc_config *cfg;	/* provided configuration */
	uint version;
	void *priv;
	uint has_init;
	int high_capacity;
	uint bus_width;
	uint clock;
	uint card_caps;
	uint ocr;
	uint dsr;
	uint dsr_imp;
	uint scr[2];
	uint csd[4];
	uint cid[4];
	ushort rca;
	u8 part_support;
	u8 part_attr;
	char part_config;
	char part_num;
	uint tran_speed;
	uint read_bl_len;
	uint write_bl_len;
	uint erase_grp_size;	/* in 512-byte sectors */
	uint hc_wp_grp_size;	/* in 512-byte sectors */
	u64 capacity;
	u64 capacity_user;
	u64 capacity_boot;
	u64 capacity_rpmb;
	u64 capacity_gp[4];
	u64 enh_user_start;
	u64 enh_user_size;
	block_dev_desc_t block_dev;
	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
	char init_in_progress;	/* 1 if we have done mmc_start_init() */
	char preinit;		/* start init as early as possible */
	uint op_cond_response;	/* the response byte from the last op_cond */
	int ddr_mode;
};

int mmc_register(struct mmc *mmc);
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
void mmc_destroy(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_getcd(struct mmc *mmc);
int board_mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
int board_mmc_getwp(struct mmc *mmc);
int mmc_set_dsr(struct mmc *mmc, u16 val);
/* Function to change the size of boot partition and rpmb partitions */
int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
					unsigned long rpmbsize);
/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
/* Functions to read / write the RPMB partition */
int mmc_rpmb_set_key(struct mmc *mmc, void *key);
int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
		  unsigned short cnt, unsigned char *key);
int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
		   unsigned short cnt, unsigned char *key);
/**
 * Start device initialization and return immediately; it does not block on
 * polling OCR (operation condition register) status.  Then you should call
 * mmc_init, which would block on polling OCR status and complete the device
 * initializatin.
 *
 * @param mmc	Pointer to a MMC device struct
 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 */
int mmc_start_init(struct mmc *mmc);

/**
 * Set preinit flag of mmc device.
 *
 * This will cause the device to be pre-inited during mmc_initialize(),
 * which may save boot time if the device is not accessed until later.
 * Some eMMC devices take 200-300ms to init, but unfortunately they
 * must be sent a series of commands to even get them to start preparing
 * for operation.
 *
 * @param mmc		Pointer to a MMC device struct
 * @param preinit	preinit flag value
 */
void mmc_set_preinit(struct mmc *mmc, int preinit);

#ifdef CONFIG_GENERIC_MMC
#ifdef CONFIG_MMC_SPI
#define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
#else
#define mmc_host_is_spi(mmc)	0
#endif
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
#else
int mmc_legacy_init(int verbose);
#endif

void board_mmc_power_init(void);
int board_mmc_init(bd_t *bis);
int cpu_mmc_init(bd_t *bis);
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);

/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif

#endif /* _MMC_H_ */
Commit	Line	Data
71f95118	1	/*
4a6ee172	2	* Copyright 2008,2010 Freescale Semiconductor, Inc
272cc70b AF	3	* Andy Fleming
	4	*
	5	* Based (loosely) on the Linux code
71f95118	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
71f95118 WD	8	*/
	9
	10	#ifndef _MMC_H_
	11	#define _MMC_H_
71f95118	12
272cc70b	13	#include <linux/list.h>
0d986e61	14	#include <linux/compiler.h>
07a2d42c	15	#include <part.h>
272cc70b AF	16
272cc70b AF	17	#define SD_VERSION_SD 0x20000
1741c64d	18	#define SD_VERSION_3 (SD_VERSION_SD \| 0x300)
64f4a619 JC	19	#define SD_VERSION_2 (SD_VERSION_SD \| 0x200)
	20	#define SD_VERSION_1_0 (SD_VERSION_SD \| 0x100)
	21	#define SD_VERSION_1_10 (SD_VERSION_SD \| 0x10a)
272cc70b AF	22	#define MMC_VERSION_MMC 0x10000
272cc70b AF	23	#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
64f4a619 JC	24	#define MMC_VERSION_1_2 (MMC_VERSION_MMC \| 0x102)
	25	#define MMC_VERSION_1_4 (MMC_VERSION_MMC \| 0x104)
	26	#define MMC_VERSION_2_2 (MMC_VERSION_MMC \| 0x202)
	27	#define MMC_VERSION_3 (MMC_VERSION_MMC \| 0x300)
	28	#define MMC_VERSION_4 (MMC_VERSION_MMC \| 0x400)
	29	#define MMC_VERSION_4_1 (MMC_VERSION_MMC \| 0x401)
	30	#define MMC_VERSION_4_2 (MMC_VERSION_MMC \| 0x402)
	31	#define MMC_VERSION_4_3 (MMC_VERSION_MMC \| 0x403)
	32	#define MMC_VERSION_4_41 (MMC_VERSION_MMC \| 0x429)
	33	#define MMC_VERSION_4_5 (MMC_VERSION_MMC \| 0x405)
edab723b	34	#define MMC_VERSION_5_0 (MMC_VERSION_MMC \| 0x500)
272cc70b	35
8caf46d1 JC	36	#define MMC_MODE_HS (1 << 0)
	37	#define MMC_MODE_HS_52MHz (1 << 1)
	38	#define MMC_MODE_4BIT (1 << 2)
	39	#define MMC_MODE_8BIT (1 << 3)
	40	#define MMC_MODE_SPI (1 << 4)
	41	#define MMC_MODE_HC (1 << 5)
d22e3d46	42	#define MMC_MODE_DDR_52MHz (1 << 6)
62722036	43
272cc70b AF	44	#define SD_DATA_4BIT 0x00040000
272cc70b AF	45
79b91de9	46	#define IS_SD(x) (x->version & SD_VERSION_SD)
272cc70b AF	47
	48	#define MMC_DATA_READ 1
	49	#define MMC_DATA_WRITE 2
	50
	51	#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
	52	#define UNUSABLE_ERR -17 /* Unusable Card */
	53	#define COMM_ERR -18 /* Communications Error */
	54	#define TIMEOUT -19
e9550449	55	#define IN_PROGRESS -20 /* operation is in progress */
6b2221b0	56	#define SWITCH_ERR -21 /* Card reports failure to switch mode */
272cc70b	57
341188b9 HS	58	#define MMC_CMD_GO_IDLE_STATE 0
	59	#define MMC_CMD_SEND_OP_COND 1
	60	#define MMC_CMD_ALL_SEND_CID 2
	61	#define MMC_CMD_SET_RELATIVE_ADDR 3
	62	#define MMC_CMD_SET_DSR 4
272cc70b	63	#define MMC_CMD_SWITCH 6
341188b9	64	#define MMC_CMD_SELECT_CARD 7
272cc70b	65	#define MMC_CMD_SEND_EXT_CSD 8
341188b9 HS	66	#define MMC_CMD_SEND_CSD 9
341188b9 HS	67	#define MMC_CMD_SEND_CID 10
272cc70b	68	#define MMC_CMD_STOP_TRANSMISSION 12
341188b9 HS	69	#define MMC_CMD_SEND_STATUS 13
	70	#define MMC_CMD_SET_BLOCKLEN 16
	71	#define MMC_CMD_READ_SINGLE_BLOCK 17
	72	#define MMC_CMD_READ_MULTIPLE_BLOCK 18
91fdabc6	73	#define MMC_CMD_SET_BLOCK_COUNT 23
272cc70b AF	74	#define MMC_CMD_WRITE_SINGLE_BLOCK 24
272cc70b AF	75	#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
e6f99a56 LW	76	#define MMC_CMD_ERASE_GROUP_START 35
	77	#define MMC_CMD_ERASE_GROUP_END 36
	78	#define MMC_CMD_ERASE 38
341188b9	79	#define MMC_CMD_APP_CMD 55
d52ebf10 TC	80	#define MMC_CMD_SPI_READ_OCR 58
d52ebf10 TC	81	#define MMC_CMD_SPI_CRC_ON_OFF 59
3690d6d6 A	82	#define MMC_CMD_RES_MAN 62
	83
	84	#define MMC_CMD62_ARG1 0xefac62ec
	85	#define MMC_CMD62_ARG2 0xcbaea7
	86
341188b9	87
341188b9	88	#define SD_CMD_SEND_RELATIVE_ADDR 3
272cc70b	89	#define SD_CMD_SWITCH_FUNC 6
341188b9 HS	90	#define SD_CMD_SEND_IF_COND 8
	91
	92	#define SD_CMD_APP_SET_BUS_WIDTH 6
e6f99a56 LW	93	#define SD_CMD_ERASE_WR_BLK_START 32
e6f99a56 LW	94	#define SD_CMD_ERASE_WR_BLK_END 33
341188b9	95	#define SD_CMD_APP_SEND_OP_COND 41
272cc70b AF	96	#define SD_CMD_APP_SEND_SCR 51
	97
	98	/* SCR definitions in different words */
	99	#define SD_HIGHSPEED_BUSY 0x00020000
	100	#define SD_HIGHSPEED_SUPPORTED 0x00020000
	101
abe2c93f TC	102	#define OCR_BUSY 0x80000000
abe2c93f TC	103	#define OCR_HCS 0x40000000
31cacbab RR	104	#define OCR_VOLTAGE_MASK 0x007FFF80
31cacbab RR	105	#define OCR_ACCESS_MODE 0x60000000
272cc70b	106
e6f99a56 LW	107	#define SECURE_ERASE 0x80000000
e6f99a56 LW	108
5d4fc8d9	109	#define MMC_STATUS_MASK (~0x0206BF7F)
6b2221b0	110	#define MMC_STATUS_SWITCH_ERROR (1 << 7)
abe2c93f TC	111	#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
abe2c93f TC	112	#define MMC_STATUS_CURR_STATE (0xf << 9)
ed018b21	113	#define MMC_STATUS_ERROR (1 << 19)
5d4fc8d9	114
d617c426 JK	115	#define MMC_STATE_PRG (7 << 9)
d617c426 JK	116
272cc70b AF	117	#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
	118	#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
	119	#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
	120	#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
	121	#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
	122	#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
	123	#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
	124	#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
	125	#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
	126	#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
	127	#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
	128	#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
	129	#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
	130	#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
	131	#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
	132	#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
	133	#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
	134
	135	#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
	136	#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
	137	addressed by index which are
	138	1 in value field */
	139	#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
	140	addressed by index, which are
	141	1 in value field */
	142	#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
	143
	144	#define SD_SWITCH_CHECK 0
	145	#define SD_SWITCH_SWITCH 1
	146
	147	/*
	148	* EXT_CSD fields
	149	*/
a7f852b6 DSC	150	#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
a7f852b6 DSC	151	#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
f866a46d	152	#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
d7b29129	153	#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
1937e5aa	154	#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
0560db18	155	#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
33ace362	156	#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
f866a46d	157	#define EXT_CSD_RPMB_MULT 168 /* RO */
0560db18	158	#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
3690d6d6	159	#define EXT_CSD_BOOT_BUS_WIDTH 177
0560db18 LW	160	#define EXT_CSD_PART_CONF 179 /* R/W */
	161	#define EXT_CSD_BUS_WIDTH 183 /* R/W */
	162	#define EXT_CSD_HS_TIMING 185 /* R/W */
	163	#define EXT_CSD_REV 192 /* RO */
	164	#define EXT_CSD_CARD_TYPE 196 /* RO */
	165	#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
f866a46d	166	#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
0560db18	167	#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
8948ea83	168	#define EXT_CSD_BOOT_MULT 226 /* RO */
272cc70b AF	169
	170	/*
	171	* EXT_CSD field definitions
	172	*/
	173
abe2c93f TC	174	#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
	175	#define EXT_CSD_CMD_SET_SECURE (1 << 1)
	176	#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
272cc70b	177
abe2c93f TC	178	#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
abe2c93f TC	179	#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
d22e3d46 JC	180	#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
	181	#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
	182	#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
	183	\| EXT_CSD_CARD_TYPE_DDR_1_2V)
272cc70b AF	184
	185	#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
	186	#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
	187	#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
d22e3d46 JC	188	#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
d22e3d46 JC	189	#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
341188b9	190
3690d6d6 A	191	#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
	192	#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
	193	#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
	194	#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
	195
	196	#define EXT_CSD_BOOT_ACK(x) (x << 6)
	197	#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
	198	#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
	199
5a99b9de TR	200	#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
	201	#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
	202	#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
3690d6d6	203
d7b29129 MN	204	#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
d7b29129 MN	205
c3dbb4f9 DSC	206	#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
	207	#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
	208
1de97f98 AF	209	#define R1_ILLEGAL_COMMAND (1 << 22)
	210	#define R1_APP_CMD (1 << 5)
	211
272cc70b	212	#define MMC_RSP_PRESENT (1 << 0)
abe2c93f TC	213	#define MMC_RSP_136 (1 << 1) /* 136 bit response */
	214	#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
	215	#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
	216	#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
272cc70b	217
abe2c93f TC	218	#define MMC_RSP_NONE (0)
abe2c93f TC	219	#define MMC_RSP_R1 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b AF	220	#define MMC_RSP_R1b (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE\| \
272cc70b AF	221	MMC_RSP_BUSY)
abe2c93f TC	222	#define MMC_RSP_R2 (MMC_RSP_PRESENT\|MMC_RSP_136\|MMC_RSP_CRC)
	223	#define MMC_RSP_R3 (MMC_RSP_PRESENT)
	224	#define MMC_RSP_R4 (MMC_RSP_PRESENT)
	225	#define MMC_RSP_R5 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	226	#define MMC_RSP_R6 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	227	#define MMC_RSP_R7 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b	228
bc897b1d LW	229	#define MMCPART_NOAVAILABLE (0xff)
	230	#define PART_ACCESS_MASK (0x7)
	231	#define PART_SUPPORT (0x1)
c3dbb4f9	232	#define ENHNCD_SUPPORT (0x2)
1937e5aa	233	#define PART_ENH_ATTRIB (0x1f)
71f95118	234
8bfa195e SG	235	/* Maximum block size for MMC */
	236	#define MMC_MAX_BLOCK_LEN 512
	237
3690d6d6 A	238	/* The number of MMC physical partitions. These consist of:
	239	* boot partitions (2), general purpose partitions (4) in MMC v4.4.
	240	*/
	241	#define MMC_NUM_BOOT_PARTITION 2
91fdabc6	242	#define MMC_PART_RPMB 3 /* RPMB partition number */
3690d6d6	243
1de97f98 AF	244	struct mmc_cid {
	245	unsigned long psn;
	246	unsigned short oid;
	247	unsigned char mid;
	248	unsigned char prv;
	249	unsigned char mdt;
	250	char pnm[7];
	251	};
	252
272cc70b AF	253	struct mmc_cmd {
	254	ushort cmdidx;
	255	uint resp_type;
	256	uint cmdarg;
0b453ffe	257	uint response[4];
272cc70b AF	258	};
	259
	260	struct mmc_data {
	261	union {
	262	char *dest;
	263	const char src; / src buffers don't get written to */
	264	};
	265	uint flags;
	266	uint blocks;
	267	uint blocksize;
	268	};
	269
ab769f22 PA	270	/* forward decl. */
	271	struct mmc;
	272
	273	struct mmc_ops {
	274	int (send_cmd)(struct mmc mmc,
	275	struct mmc_cmd cmd, struct mmc_data data);
	276	void (set_ios)(struct mmc mmc);
	277	int (init)(struct mmc mmc);
	278	int (getcd)(struct mmc mmc);
	279	int (getwp)(struct mmc mmc);
	280	};
	281
93bfd616 PA	282	struct mmc_config {
	283	const char *name;
	284	const struct mmc_ops *ops;
	285	uint host_caps;
	286	uint voltages;
	287	uint f_min;
	288	uint f_max;
	289	uint b_max;
	290	unsigned char part_type;
	291	};
	292
	293	/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
272cc70b AF	294	struct mmc {
272cc70b AF	295	struct list_head link;
93bfd616	296	const struct mmc_config cfg; / provided configuration */
272cc70b	297	uint version;
93bfd616	298	void *priv;
bc897b1d	299	uint has_init;
272cc70b AF	300	int high_capacity;
	301	uint bus_width;
	302	uint clock;
	303	uint card_caps;
272cc70b	304	uint ocr;
ab71188c MN	305	uint dsr;
ab71188c MN	306	uint dsr_imp;
272cc70b AF	307	uint scr[2];
272cc70b AF	308	uint csd[4];
0b453ffe	309	uint cid[4];
272cc70b	310	ushort rca;
c3dbb4f9 DSC	311	u8 part_support;
c3dbb4f9 DSC	312	u8 part_attr;
bc897b1d LW	313	char part_config;
bc897b1d LW	314	char part_num;
272cc70b AF	315	uint tran_speed;
	316	uint read_bl_len;
	317	uint write_bl_len;
a4ff9f83	318	uint erase_grp_size; /* in 512-byte sectors */
037dc0ab	319	uint hc_wp_grp_size; /* in 512-byte sectors */
272cc70b	320	u64 capacity;
f866a46d SW	321	u64 capacity_user;
	322	u64 capacity_boot;
	323	u64 capacity_rpmb;
	324	u64 capacity_gp[4];
a7f852b6 DSC	325	u64 enh_user_start;
a7f852b6 DSC	326	u64 enh_user_size;
272cc70b	327	block_dev_desc_t block_dev;
e9550449 CLC	328	char op_cond_pending; /* 1 if we are waiting on an op_cond command */
	329	char init_in_progress; /* 1 if we have done mmc_start_init() */
	330	char preinit; /* start init as early as possible */
	331	uint op_cond_response; /* the response byte from the last op_cond */
786e8f81	332	int ddr_mode;
272cc70b AF	333	};
	334
	335	int mmc_register(struct mmc *mmc);
93bfd616 PA	336	struct mmc mmc_create(const struct mmc_config cfg, void *priv);
93bfd616 PA	337	void mmc_destroy(struct mmc *mmc);
272cc70b AF	338	int mmc_initialize(bd_t *bis);
	339	int mmc_init(struct mmc *mmc);
	340	int mmc_read(struct mmc mmc, u64 src, uchar dst, int size);
4a6ee172	341	void mmc_set_clock(struct mmc *mmc, uint clock);
272cc70b	342	struct mmc *find_mmc_device(int dev_num);
89716964	343	int mmc_set_dev(int dev_num);
272cc70b	344	void print_mmc_devices(char separator);
ea6ebe21	345	int get_mmc_num(void);
bc897b1d	346	int mmc_switch_part(int dev_num, unsigned int part_num);
48972d90	347	int mmc_getcd(struct mmc *mmc);
750121c3	348	int board_mmc_getcd(struct mmc *mmc);
d23d8d7e	349	int mmc_getwp(struct mmc *mmc);
750121c3	350	int board_mmc_getwp(struct mmc *mmc);
ab71188c	351	int mmc_set_dsr(struct mmc *mmc, u16 val);
3690d6d6 A	352	/* Function to change the size of boot partition and rpmb partitions */
	353	int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
	354	unsigned long rpmbsize);
792970b0 TR	355	/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
792970b0 TR	356	int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
5a99b9de TR	357	/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
5a99b9de TR	358	int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
33ace362 TR	359	/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
33ace362 TR	360	int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
91fdabc6 PA	361	/* Functions to read / write the RPMB partition */
	362	int mmc_rpmb_set_key(struct mmc mmc, void key);
	363	int mmc_rpmb_get_counter(struct mmc mmc, unsigned long counter);
	364	int mmc_rpmb_read(struct mmc mmc, void addr, unsigned short blk,
	365	unsigned short cnt, unsigned char *key);
	366	int mmc_rpmb_write(struct mmc mmc, void addr, unsigned short blk,
	367	unsigned short cnt, unsigned char *key);
e9550449 CLC	368	/**
	369	* Start device initialization and return immediately; it does not block on
	370	* polling OCR (operation condition register) status. Then you should call
	371	* mmc_init, which would block on polling OCR status and complete the device
	372	* initializatin.
	373	*
	374	* @param mmc Pointer to a MMC device struct
	375	* @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
	376	*/
	377	int mmc_start_init(struct mmc *mmc);
	378
	379	/**
	380	* Set preinit flag of mmc device.
	381	*
	382	* This will cause the device to be pre-inited during mmc_initialize(),
	383	* which may save boot time if the device is not accessed until later.
	384	* Some eMMC devices take 200-300ms to init, but unfortunately they
	385	* must be sent a series of commands to even get them to start preparing
	386	* for operation.
	387	*
	388	* @param mmc Pointer to a MMC device struct
	389	* @param preinit preinit flag value
	390	*/
	391	void mmc_set_preinit(struct mmc *mmc, int preinit);
	392
1592ef85	393	#ifdef CONFIG_GENERIC_MMC
8687d5c8	394	#ifdef CONFIG_MMC_SPI
0b2da7e2	395	#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
8687d5c8 PB	396	#else
	397	#define mmc_host_is_spi(mmc) 0
	398	#endif
d52ebf10	399	struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
1592ef85	400	#else
272cc70b AF	401	int mmc_legacy_init(int verbose);
272cc70b AF	402	#endif
1592ef85	403
95de9ab2	404	void board_mmc_power_init(void);
3c7ca967	405	int board_mmc_init(bd_t *bis);
750121c3	406	int cpu_mmc_init(bd_t *bis);
aeb80555	407	int mmc_get_env_addr(struct mmc mmc, int copy, u32 env_addr);
3c7ca967	408
93bfd616 PA	409	/* Set block count limit because of 16 bit register limit on some hardware*/
	410	#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
	411	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
	412	#endif
	413
71f95118	414	#endif /* _MMC_H_ */