[people/ms/u-boot.git] / include / mmc.h

/*
 * Copyright 2008,2010 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based (loosely) on the Linux code
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _MMC_H_
#define _MMC_H_

#include <linux/list.h>
#include <linux/compiler.h>

#define SD_VERSION_SD	0x20000
#define SD_VERSION_3	(SD_VERSION_SD | 0x300)
#define SD_VERSION_2	(SD_VERSION_SD | 0x200)
#define SD_VERSION_1_0	(SD_VERSION_SD | 0x100)
#define SD_VERSION_1_10	(SD_VERSION_SD | 0x10a)
#define MMC_VERSION_MMC		0x10000
#define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x102)
#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x104)
#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x202)
#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x300)
#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x400)
#define MMC_VERSION_4_1		(MMC_VERSION_MMC | 0x401)
#define MMC_VERSION_4_2		(MMC_VERSION_MMC | 0x402)
#define MMC_VERSION_4_3		(MMC_VERSION_MMC | 0x403)
#define MMC_VERSION_4_41	(MMC_VERSION_MMC | 0x429)
#define MMC_VERSION_4_5		(MMC_VERSION_MMC | 0x405)

#define MMC_MODE_HS		0x001
#define MMC_MODE_HS_52MHz	0x010
#define MMC_MODE_4BIT		0x100
#define MMC_MODE_8BIT		0x200
#define MMC_MODE_SPI		0x400
#define MMC_MODE_HC		0x800

#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
#define MMC_MODE_WIDTH_BITS_SHIFT 8

#define SD_DATA_4BIT	0x00040000

#define IS_SD(x) (x->version & SD_VERSION_SD)

#define MMC_DATA_READ		1
#define MMC_DATA_WRITE		2

#define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
#define UNUSABLE_ERR		-17 /* Unusable Card */
#define COMM_ERR		-18 /* Communications Error */
#define TIMEOUT			-19
#define IN_PROGRESS		-20 /* operation is in progress */

#define MMC_CMD_GO_IDLE_STATE		0
#define MMC_CMD_SEND_OP_COND		1
#define MMC_CMD_ALL_SEND_CID		2
#define MMC_CMD_SET_RELATIVE_ADDR	3
#define MMC_CMD_SET_DSR			4
#define MMC_CMD_SWITCH			6
#define MMC_CMD_SELECT_CARD		7
#define MMC_CMD_SEND_EXT_CSD		8
#define MMC_CMD_SEND_CSD		9
#define MMC_CMD_SEND_CID		10
#define MMC_CMD_STOP_TRANSMISSION	12
#define MMC_CMD_SEND_STATUS		13
#define MMC_CMD_SET_BLOCKLEN		16
#define MMC_CMD_READ_SINGLE_BLOCK	17
#define MMC_CMD_READ_MULTIPLE_BLOCK	18
#define MMC_CMD_WRITE_SINGLE_BLOCK	24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
#define MMC_CMD_ERASE_GROUP_START	35
#define MMC_CMD_ERASE_GROUP_END		36
#define MMC_CMD_ERASE			38
#define MMC_CMD_APP_CMD			55
#define MMC_CMD_SPI_READ_OCR		58
#define MMC_CMD_SPI_CRC_ON_OFF		59
#define MMC_CMD_RES_MAN			62

#define MMC_CMD62_ARG1			0xefac62ec
#define MMC_CMD62_ARG2			0xcbaea7


#define SD_CMD_SEND_RELATIVE_ADDR	3
#define SD_CMD_SWITCH_FUNC		6
#define SD_CMD_SEND_IF_COND		8

#define SD_CMD_APP_SET_BUS_WIDTH	6
#define SD_CMD_ERASE_WR_BLK_START	32
#define SD_CMD_ERASE_WR_BLK_END		33
#define SD_CMD_APP_SEND_OP_COND		41
#define SD_CMD_APP_SEND_SCR		51

/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY	0x00020000
#define SD_HIGHSPEED_SUPPORTED	0x00020000

#define MMC_HS_TIMING		0x00000100
#define MMC_HS_52MHZ		0x2

#define OCR_BUSY		0x80000000
#define OCR_HCS			0x40000000
#define OCR_VOLTAGE_MASK	0x007FFF80
#define OCR_ACCESS_MODE		0x60000000

#define SECURE_ERASE		0x80000000

#define MMC_STATUS_MASK		(~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE	(0xf << 9)
#define MMC_STATUS_ERROR	(1 << 19)

#define MMC_STATE_PRG		(7 << 9)

#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */

#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
						addressed by index which are
						1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
						addressed by index, which are
						1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */

#define SD_SWITCH_CHECK		0
#define SD_SWITCH_SWITCH	1

/*
 * EXT_CSD fields
 */
#define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
#define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
#define EXT_CSD_RPMB_MULT		168	/* RO */
#define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
#define EXT_CSD_BOOT_BUS_WIDTH		177
#define EXT_CSD_PART_CONF		179	/* R/W */
#define EXT_CSD_BUS_WIDTH		183	/* R/W */
#define EXT_CSD_HS_TIMING		185	/* R/W */
#define EXT_CSD_REV			192	/* RO */
#define EXT_CSD_CARD_TYPE		196	/* RO */
#define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
#define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
#define EXT_CSD_BOOT_MULT		226	/* RO */

/*
 * EXT_CSD field definitions
 */

#define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
#define EXT_CSD_CMD_SET_SECURE		(1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)

#define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */

#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */

#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)

#define EXT_CSD_BOOT_ACK(x)		(x << 6)
#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)

#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)

#define R1_ILLEGAL_COMMAND		(1 << 22)
#define R1_APP_CMD			(1 << 5)

#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */

#define MMC_RSP_NONE	(0)
#define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
			MMC_RSP_BUSY)
#define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3	(MMC_RSP_PRESENT)
#define MMC_RSP_R4	(MMC_RSP_PRESENT)
#define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)

#define MMCPART_NOAVAILABLE	(0xff)
#define PART_ACCESS_MASK	(0x7)
#define PART_SUPPORT		(0x1)
#define PART_ENH_ATTRIB		(0x1f)

/* Maximum block size for MMC */
#define MMC_MAX_BLOCK_LEN	512

/* The number of MMC physical partitions.  These consist of:
 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 */
#define MMC_NUM_BOOT_PARTITION	2

struct mmc_cid {
	unsigned long psn;
	unsigned short oid;
	unsigned char mid;
	unsigned char prv;
	unsigned char mdt;
	char pnm[7];
};

struct mmc_cmd {
	ushort cmdidx;
	uint resp_type;
	uint cmdarg;
	uint response[4];
};

struct mmc_data {
	union {
		char *dest;
		const char *src; /* src buffers don't get written to */
	};
	uint flags;
	uint blocks;
	uint blocksize;
};

/* forward decl. */
struct mmc;

struct mmc_ops {
	int (*send_cmd)(struct mmc *mmc,
			struct mmc_cmd *cmd, struct mmc_data *data);
	void (*set_ios)(struct mmc *mmc);
	int (*init)(struct mmc *mmc);
	int (*getcd)(struct mmc *mmc);
	int (*getwp)(struct mmc *mmc);
};

struct mmc {
	struct list_head link;
	char name[32];
	void *priv;
	uint voltages;
	uint version;
	uint has_init;
	uint f_min;
	uint f_max;
	int high_capacity;
	uint bus_width;
	uint clock;
	uint card_caps;
	uint host_caps;
	uint ocr;
	uint dsr;
	uint dsr_imp;
	uint scr[2];
	uint csd[4];
	uint cid[4];
	ushort rca;
	char part_config;
	char part_num;
	uint tran_speed;
	uint read_bl_len;
	uint write_bl_len;
	uint erase_grp_size;
	u64 capacity;
	u64 capacity_user;
	u64 capacity_boot;
	u64 capacity_rpmb;
	u64 capacity_gp[4];
	block_dev_desc_t block_dev;
	const struct mmc_ops *ops;
	uint b_max;
	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
	char init_in_progress;	/* 1 if we have done mmc_start_init() */
	char preinit;		/* start init as early as possible */
	uint op_cond_response;	/* the response byte from the last op_cond */
};

int mmc_register(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
int board_mmc_getcd(struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
int mmc_set_dsr(struct mmc *mmc, u16 val);
/* Function to change the size of boot partition and rpmb partitions */
int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
					unsigned long rpmbsize);
/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);

/**
 * Start device initialization and return immediately; it does not block on
 * polling OCR (operation condition register) status.  Then you should call
 * mmc_init, which would block on polling OCR status and complete the device
 * initializatin.
 *
 * @param mmc	Pointer to a MMC device struct
 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 */
int mmc_start_init(struct mmc *mmc);

/**
 * Set preinit flag of mmc device.
 *
 * This will cause the device to be pre-inited during mmc_initialize(),
 * which may save boot time if the device is not accessed until later.
 * Some eMMC devices take 200-300ms to init, but unfortunately they
 * must be sent a series of commands to even get them to start preparing
 * for operation.
 *
 * @param mmc		Pointer to a MMC device struct
 * @param preinit	preinit flag value
 */
void mmc_set_preinit(struct mmc *mmc, int preinit);

#ifdef CONFIG_GENERIC_MMC
#ifdef CONFIG_MMC_SPI
#define mmc_host_is_spi(mmc)	((mmc)->host_caps & MMC_MODE_SPI)
#else
#define mmc_host_is_spi(mmc)	0
#endif
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
#else
int mmc_legacy_init(int verbose);
#endif

#endif /* _MMC_H_ */
Commit	Line	Data
71f95118	1	/*
4a6ee172	2	* Copyright 2008,2010 Freescale Semiconductor, Inc
272cc70b AF	3	* Andy Fleming
	4	*
	5	* Based (loosely) on the Linux code
71f95118	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
71f95118 WD	8	*/
	9
	10	#ifndef _MMC_H_
	11	#define _MMC_H_
71f95118	12
272cc70b	13	#include <linux/list.h>
0d986e61	14	#include <linux/compiler.h>
272cc70b AF	15
272cc70b AF	16	#define SD_VERSION_SD 0x20000
1741c64d	17	#define SD_VERSION_3 (SD_VERSION_SD \| 0x300)
64f4a619 JC	18	#define SD_VERSION_2 (SD_VERSION_SD \| 0x200)
	19	#define SD_VERSION_1_0 (SD_VERSION_SD \| 0x100)
	20	#define SD_VERSION_1_10 (SD_VERSION_SD \| 0x10a)
272cc70b AF	21	#define MMC_VERSION_MMC 0x10000
272cc70b AF	22	#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
64f4a619 JC	23	#define MMC_VERSION_1_2 (MMC_VERSION_MMC \| 0x102)
	24	#define MMC_VERSION_1_4 (MMC_VERSION_MMC \| 0x104)
	25	#define MMC_VERSION_2_2 (MMC_VERSION_MMC \| 0x202)
	26	#define MMC_VERSION_3 (MMC_VERSION_MMC \| 0x300)
	27	#define MMC_VERSION_4 (MMC_VERSION_MMC \| 0x400)
	28	#define MMC_VERSION_4_1 (MMC_VERSION_MMC \| 0x401)
	29	#define MMC_VERSION_4_2 (MMC_VERSION_MMC \| 0x402)
	30	#define MMC_VERSION_4_3 (MMC_VERSION_MMC \| 0x403)
	31	#define MMC_VERSION_4_41 (MMC_VERSION_MMC \| 0x429)
	32	#define MMC_VERSION_4_5 (MMC_VERSION_MMC \| 0x405)
272cc70b AF	33
	34	#define MMC_MODE_HS 0x001
	35	#define MMC_MODE_HS_52MHz 0x010
	36	#define MMC_MODE_4BIT 0x100
	37	#define MMC_MODE_8BIT 0x200
d52ebf10	38	#define MMC_MODE_SPI 0x400
b1f1e821	39	#define MMC_MODE_HC 0x800
272cc70b	40
62722036 ŁM	41	#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT \| MMC_MODE_8BIT)
	42	#define MMC_MODE_WIDTH_BITS_SHIFT 8
	43
272cc70b AF	44	#define SD_DATA_4BIT 0x00040000
272cc70b AF	45
79b91de9	46	#define IS_SD(x) (x->version & SD_VERSION_SD)
272cc70b AF	47
	48	#define MMC_DATA_READ 1
	49	#define MMC_DATA_WRITE 2
	50
	51	#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
	52	#define UNUSABLE_ERR -17 /* Unusable Card */
	53	#define COMM_ERR -18 /* Communications Error */
	54	#define TIMEOUT -19
e9550449	55	#define IN_PROGRESS -20 /* operation is in progress */
272cc70b	56
341188b9 HS	57	#define MMC_CMD_GO_IDLE_STATE 0
	58	#define MMC_CMD_SEND_OP_COND 1
	59	#define MMC_CMD_ALL_SEND_CID 2
	60	#define MMC_CMD_SET_RELATIVE_ADDR 3
	61	#define MMC_CMD_SET_DSR 4
272cc70b	62	#define MMC_CMD_SWITCH 6
341188b9	63	#define MMC_CMD_SELECT_CARD 7
272cc70b	64	#define MMC_CMD_SEND_EXT_CSD 8
341188b9 HS	65	#define MMC_CMD_SEND_CSD 9
341188b9 HS	66	#define MMC_CMD_SEND_CID 10
272cc70b	67	#define MMC_CMD_STOP_TRANSMISSION 12
341188b9 HS	68	#define MMC_CMD_SEND_STATUS 13
	69	#define MMC_CMD_SET_BLOCKLEN 16
	70	#define MMC_CMD_READ_SINGLE_BLOCK 17
	71	#define MMC_CMD_READ_MULTIPLE_BLOCK 18
272cc70b AF	72	#define MMC_CMD_WRITE_SINGLE_BLOCK 24
272cc70b AF	73	#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
e6f99a56 LW	74	#define MMC_CMD_ERASE_GROUP_START 35
	75	#define MMC_CMD_ERASE_GROUP_END 36
	76	#define MMC_CMD_ERASE 38
341188b9	77	#define MMC_CMD_APP_CMD 55
d52ebf10 TC	78	#define MMC_CMD_SPI_READ_OCR 58
d52ebf10 TC	79	#define MMC_CMD_SPI_CRC_ON_OFF 59
3690d6d6 A	80	#define MMC_CMD_RES_MAN 62
	81
	82	#define MMC_CMD62_ARG1 0xefac62ec
	83	#define MMC_CMD62_ARG2 0xcbaea7
	84
341188b9	85
341188b9	86	#define SD_CMD_SEND_RELATIVE_ADDR 3
272cc70b	87	#define SD_CMD_SWITCH_FUNC 6
341188b9 HS	88	#define SD_CMD_SEND_IF_COND 8
	89
	90	#define SD_CMD_APP_SET_BUS_WIDTH 6
e6f99a56 LW	91	#define SD_CMD_ERASE_WR_BLK_START 32
e6f99a56 LW	92	#define SD_CMD_ERASE_WR_BLK_END 33
341188b9	93	#define SD_CMD_APP_SEND_OP_COND 41
272cc70b AF	94	#define SD_CMD_APP_SEND_SCR 51
	95
	96	/* SCR definitions in different words */
	97	#define SD_HIGHSPEED_BUSY 0x00020000
	98	#define SD_HIGHSPEED_SUPPORTED 0x00020000
	99
	100	#define MMC_HS_TIMING 0x00000100
	101	#define MMC_HS_52MHZ 0x2
	102
abe2c93f TC	103	#define OCR_BUSY 0x80000000
abe2c93f TC	104	#define OCR_HCS 0x40000000
31cacbab RR	105	#define OCR_VOLTAGE_MASK 0x007FFF80
31cacbab RR	106	#define OCR_ACCESS_MODE 0x60000000
272cc70b	107
e6f99a56 LW	108	#define SECURE_ERASE 0x80000000
e6f99a56 LW	109
5d4fc8d9	110	#define MMC_STATUS_MASK (~0x0206BF7F)
abe2c93f TC	111	#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
abe2c93f TC	112	#define MMC_STATUS_CURR_STATE (0xf << 9)
ed018b21	113	#define MMC_STATUS_ERROR (1 << 19)
5d4fc8d9	114
d617c426 JK	115	#define MMC_STATE_PRG (7 << 9)
d617c426 JK	116
272cc70b AF	117	#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
	118	#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
	119	#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
	120	#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
	121	#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
	122	#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
	123	#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
	124	#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
	125	#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
	126	#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
	127	#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
	128	#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
	129	#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
	130	#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
	131	#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
	132	#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
	133	#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
	134
	135	#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
	136	#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
	137	addressed by index which are
	138	1 in value field */
	139	#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
	140	addressed by index, which are
	141	1 in value field */
	142	#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
	143
	144	#define SD_SWITCH_CHECK 0
	145	#define SD_SWITCH_SWITCH 1
	146
	147	/*
	148	* EXT_CSD fields
	149	*/
f866a46d	150	#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
1937e5aa	151	#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
0560db18	152	#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
f866a46d	153	#define EXT_CSD_RPMB_MULT 168 /* RO */
0560db18	154	#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
3690d6d6	155	#define EXT_CSD_BOOT_BUS_WIDTH 177
0560db18 LW	156	#define EXT_CSD_PART_CONF 179 /* R/W */
	157	#define EXT_CSD_BUS_WIDTH 183 /* R/W */
	158	#define EXT_CSD_HS_TIMING 185 /* R/W */
	159	#define EXT_CSD_REV 192 /* RO */
	160	#define EXT_CSD_CARD_TYPE 196 /* RO */
	161	#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
f866a46d	162	#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
0560db18	163	#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
8948ea83	164	#define EXT_CSD_BOOT_MULT 226 /* RO */
272cc70b AF	165
	166	/*
	167	* EXT_CSD field definitions
	168	*/
	169
abe2c93f TC	170	#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
	171	#define EXT_CSD_CMD_SET_SECURE (1 << 1)
	172	#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
272cc70b	173
abe2c93f TC	174	#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
abe2c93f TC	175	#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
272cc70b AF	176
	177	#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
	178	#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
	179	#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
341188b9	180
3690d6d6 A	181	#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
	182	#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
	183	#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
	184	#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
	185
	186	#define EXT_CSD_BOOT_ACK(x) (x << 6)
	187	#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
	188	#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
	189
5a99b9de TR	190	#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
	191	#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
	192	#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
3690d6d6	193
1de97f98 AF	194	#define R1_ILLEGAL_COMMAND (1 << 22)
	195	#define R1_APP_CMD (1 << 5)
	196
272cc70b	197	#define MMC_RSP_PRESENT (1 << 0)
abe2c93f TC	198	#define MMC_RSP_136 (1 << 1) /* 136 bit response */
	199	#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
	200	#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
	201	#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
272cc70b	202
abe2c93f TC	203	#define MMC_RSP_NONE (0)
abe2c93f TC	204	#define MMC_RSP_R1 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b AF	205	#define MMC_RSP_R1b (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE\| \
272cc70b AF	206	MMC_RSP_BUSY)
abe2c93f TC	207	#define MMC_RSP_R2 (MMC_RSP_PRESENT\|MMC_RSP_136\|MMC_RSP_CRC)
	208	#define MMC_RSP_R3 (MMC_RSP_PRESENT)
	209	#define MMC_RSP_R4 (MMC_RSP_PRESENT)
	210	#define MMC_RSP_R5 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	211	#define MMC_RSP_R6 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	212	#define MMC_RSP_R7 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b	213
bc897b1d LW	214	#define MMCPART_NOAVAILABLE (0xff)
	215	#define PART_ACCESS_MASK (0x7)
	216	#define PART_SUPPORT (0x1)
1937e5aa	217	#define PART_ENH_ATTRIB (0x1f)
71f95118	218
8bfa195e SG	219	/* Maximum block size for MMC */
	220	#define MMC_MAX_BLOCK_LEN 512
	221
3690d6d6 A	222	/* The number of MMC physical partitions. These consist of:
	223	* boot partitions (2), general purpose partitions (4) in MMC v4.4.
	224	*/
	225	#define MMC_NUM_BOOT_PARTITION 2
	226
1de97f98 AF	227	struct mmc_cid {
	228	unsigned long psn;
	229	unsigned short oid;
	230	unsigned char mid;
	231	unsigned char prv;
	232	unsigned char mdt;
	233	char pnm[7];
	234	};
	235
272cc70b AF	236	struct mmc_cmd {
	237	ushort cmdidx;
	238	uint resp_type;
	239	uint cmdarg;
0b453ffe	240	uint response[4];
272cc70b AF	241	};
	242
	243	struct mmc_data {
	244	union {
	245	char *dest;
	246	const char src; / src buffers don't get written to */
	247	};
	248	uint flags;
	249	uint blocks;
	250	uint blocksize;
	251	};
	252
ab769f22 PA	253	/* forward decl. */
	254	struct mmc;
	255
	256	struct mmc_ops {
	257	int (send_cmd)(struct mmc mmc,
	258	struct mmc_cmd cmd, struct mmc_data data);
	259	void (set_ios)(struct mmc mmc);
	260	int (init)(struct mmc mmc);
	261	int (getcd)(struct mmc mmc);
	262	int (getwp)(struct mmc mmc);
	263	};
	264
272cc70b AF	265	struct mmc {
	266	struct list_head link;
	267	char name[32];
	268	void *priv;
	269	uint voltages;
	270	uint version;
bc897b1d	271	uint has_init;
272cc70b AF	272	uint f_min;
	273	uint f_max;
	274	int high_capacity;
	275	uint bus_width;
	276	uint clock;
	277	uint card_caps;
	278	uint host_caps;
	279	uint ocr;
ab71188c MN	280	uint dsr;
ab71188c MN	281	uint dsr_imp;
272cc70b AF	282	uint scr[2];
272cc70b AF	283	uint csd[4];
0b453ffe	284	uint cid[4];
272cc70b	285	ushort rca;
bc897b1d LW	286	char part_config;
bc897b1d LW	287	char part_num;
272cc70b AF	288	uint tran_speed;
	289	uint read_bl_len;
	290	uint write_bl_len;
e6f99a56	291	uint erase_grp_size;
272cc70b	292	u64 capacity;
f866a46d SW	293	u64 capacity_user;
	294	u64 capacity_boot;
	295	u64 capacity_rpmb;
	296	u64 capacity_gp[4];
272cc70b	297	block_dev_desc_t block_dev;
ab769f22	298	const struct mmc_ops *ops;
57418d21	299	uint b_max;
e9550449 CLC	300	char op_cond_pending; /* 1 if we are waiting on an op_cond command */
	301	char init_in_progress; /* 1 if we have done mmc_start_init() */
	302	char preinit; /* start init as early as possible */
	303	uint op_cond_response; /* the response byte from the last op_cond */
272cc70b AF	304	};
	305
	306	int mmc_register(struct mmc *mmc);
	307	int mmc_initialize(bd_t *bis);
	308	int mmc_init(struct mmc *mmc);
	309	int mmc_read(struct mmc mmc, u64 src, uchar dst, int size);
4a6ee172	310	void mmc_set_clock(struct mmc *mmc, uint clock);
272cc70b	311	struct mmc *find_mmc_device(int dev_num);
89716964	312	int mmc_set_dev(int dev_num);
272cc70b	313	void print_mmc_devices(char separator);
ea6ebe21	314	int get_mmc_num(void);
314284b1	315	int board_mmc_getcd(struct mmc *mmc);
bc897b1d	316	int mmc_switch_part(int dev_num, unsigned int part_num);
48972d90	317	int mmc_getcd(struct mmc *mmc);
d23d8d7e	318	int mmc_getwp(struct mmc *mmc);
ab71188c	319	int mmc_set_dsr(struct mmc *mmc, u16 val);
3690d6d6 A	320	/* Function to change the size of boot partition and rpmb partitions */
	321	int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
	322	unsigned long rpmbsize);
792970b0 TR	323	/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
792970b0 TR	324	int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
5a99b9de TR	325	/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
5a99b9de TR	326	int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
272cc70b	327
e9550449 CLC	328	/**
	329	* Start device initialization and return immediately; it does not block on
	330	* polling OCR (operation condition register) status. Then you should call
	331	* mmc_init, which would block on polling OCR status and complete the device
	332	* initializatin.
	333	*
	334	* @param mmc Pointer to a MMC device struct
	335	* @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
	336	*/
	337	int mmc_start_init(struct mmc *mmc);
	338
	339	/**
	340	* Set preinit flag of mmc device.
	341	*
	342	* This will cause the device to be pre-inited during mmc_initialize(),
	343	* which may save boot time if the device is not accessed until later.
	344	* Some eMMC devices take 200-300ms to init, but unfortunately they
	345	* must be sent a series of commands to even get them to start preparing
	346	* for operation.
	347	*
	348	* @param mmc Pointer to a MMC device struct
	349	* @param preinit preinit flag value
	350	*/
	351	void mmc_set_preinit(struct mmc *mmc, int preinit);
	352
1592ef85	353	#ifdef CONFIG_GENERIC_MMC
8687d5c8	354	#ifdef CONFIG_MMC_SPI
d52ebf10	355	#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
8687d5c8 PB	356	#else
	357	#define mmc_host_is_spi(mmc) 0
	358	#endif
d52ebf10	359	struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
1592ef85	360	#else
272cc70b AF	361	int mmc_legacy_init(int verbose);
272cc70b AF	362	#endif
1592ef85	363
71f95118	364	#endif /* _MMC_H_ */