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324f6cfd WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
228f29ac WD |
22 | * |
23 | * Be sure to mark tests to be run before relocation as such with the | |
6d0f6bcf | 24 | * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the |
228f29ac | 25 | * logbuffer support is enabled. |
324f6cfd WD |
26 | */ |
27 | ||
28 | #include <common.h> | |
29 | ||
324f6cfd WD |
30 | #include <post.h> |
31 | ||
6e8ec682 | 32 | extern int ocm_post_test (int flags); |
324f6cfd WD |
33 | extern int cache_post_test (int flags); |
34 | extern int watchdog_post_test (int flags); | |
35 | extern int i2c_post_test (int flags); | |
36 | extern int rtc_post_test (int flags); | |
37 | extern int memory_post_test (int flags); | |
38 | extern int cpu_post_test (int flags); | |
a11e0696 | 39 | extern int fpu_post_test (int flags); |
324f6cfd WD |
40 | extern int uart_post_test (int flags); |
41 | extern int ether_post_test (int flags); | |
42 | extern int spi_post_test (int flags); | |
43 | extern int usb_post_test (int flags); | |
44 | extern int spr_post_test (int flags); | |
4532cb69 | 45 | extern int sysmon_post_test (int flags); |
5a8c51cd | 46 | extern int dsp_post_test (int flags); |
79fa88f3 | 47 | extern int codec_post_test (int flags); |
531e3e8b | 48 | extern int ecc_post_test (int flags); |
4532cb69 | 49 | |
65b20dce YT |
50 | extern int dspic_init_post_test (int flags); |
51 | extern int dspic_post_test (int flags); | |
52 | extern int gdc_post_test (int flags); | |
53 | extern int fpga_post_test (int flags); | |
54 | extern int lwmon5_watchdog_post_test(int flags); | |
55 | extern int sysmon1_post_test(int flags); | |
56 | ||
4532cb69 WD |
57 | extern int sysmon_init_f (void); |
58 | ||
59 | extern void sysmon_reloc (void); | |
60 | ||
324f6cfd WD |
61 | |
62 | struct post_test post_list[] = | |
63 | { | |
6d0f6bcf | 64 | #if CONFIG_POST & CONFIG_SYS_POST_OCM |
6e8ec682 YT |
65 | { |
66 | "OCM test", | |
67 | "ocm", | |
68 | "This test checks on chip memory (OCM).", | |
7845d490 | 69 | POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP, |
6e8ec682 YT |
70 | &ocm_post_test, |
71 | NULL, | |
72 | NULL, | |
6d0f6bcf | 73 | CONFIG_SYS_POST_OCM |
6e8ec682 YT |
74 | }, |
75 | #endif | |
6d0f6bcf | 76 | #if CONFIG_POST & CONFIG_SYS_POST_CACHE |
324f6cfd | 77 | { |
8bde7f77 WD |
78 | "Cache test", |
79 | "cache", | |
80 | "This test verifies the CPU cache operation.", | |
81 | POST_RAM | POST_ALWAYS, | |
82 | &cache_post_test, | |
83 | NULL, | |
84 | NULL, | |
6d0f6bcf | 85 | CONFIG_SYS_POST_CACHE |
324f6cfd WD |
86 | }, |
87 | #endif | |
6d0f6bcf | 88 | #if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG |
65b20dce YT |
89 | #if defined(CONFIG_POST_WATCHDOG) |
90 | CONFIG_POST_WATCHDOG, | |
91 | #else | |
324f6cfd | 92 | { |
8bde7f77 WD |
93 | "Watchdog timer test", |
94 | "watchdog", | |
95 | "This test checks the watchdog timer.", | |
8564acf9 | 96 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, |
8bde7f77 WD |
97 | &watchdog_post_test, |
98 | NULL, | |
99 | NULL, | |
6d0f6bcf | 100 | CONFIG_SYS_POST_WATCHDOG |
324f6cfd WD |
101 | }, |
102 | #endif | |
65b20dce | 103 | #endif |
6d0f6bcf | 104 | #if CONFIG_POST & CONFIG_SYS_POST_I2C |
324f6cfd | 105 | { |
8bde7f77 WD |
106 | "I2C test", |
107 | "i2c", | |
108 | "This test verifies the I2C operation.", | |
109 | POST_RAM | POST_ALWAYS, | |
110 | &i2c_post_test, | |
111 | NULL, | |
112 | NULL, | |
6d0f6bcf | 113 | CONFIG_SYS_POST_I2C |
324f6cfd WD |
114 | }, |
115 | #endif | |
6d0f6bcf | 116 | #if CONFIG_POST & CONFIG_SYS_POST_RTC |
324f6cfd | 117 | { |
8bde7f77 WD |
118 | "RTC test", |
119 | "rtc", | |
120 | "This test verifies the RTC operation.", | |
8564acf9 | 121 | POST_RAM | POST_SLOWTEST | POST_MANUAL, |
8bde7f77 WD |
122 | &rtc_post_test, |
123 | NULL, | |
124 | NULL, | |
6d0f6bcf | 125 | CONFIG_SYS_POST_RTC |
324f6cfd WD |
126 | }, |
127 | #endif | |
6d0f6bcf | 128 | #if CONFIG_POST & CONFIG_SYS_POST_MEMORY |
324f6cfd | 129 | { |
8bde7f77 WD |
130 | "Memory test", |
131 | "memory", | |
132 | "This test checks RAM.", | |
8564acf9 | 133 | POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL, |
8bde7f77 WD |
134 | &memory_post_test, |
135 | NULL, | |
136 | NULL, | |
6d0f6bcf | 137 | CONFIG_SYS_POST_MEMORY |
324f6cfd WD |
138 | }, |
139 | #endif | |
6d0f6bcf | 140 | #if CONFIG_POST & CONFIG_SYS_POST_CPU |
324f6cfd | 141 | { |
8bde7f77 WD |
142 | "CPU test", |
143 | "cpu", | |
144 | "This test verifies the arithmetic logic unit of" | |
145 | " CPU.", | |
146 | POST_RAM | POST_ALWAYS, | |
147 | &cpu_post_test, | |
148 | NULL, | |
149 | NULL, | |
6d0f6bcf | 150 | CONFIG_SYS_POST_CPU |
324f6cfd WD |
151 | }, |
152 | #endif | |
6d0f6bcf | 153 | #if CONFIG_POST & CONFIG_SYS_POST_FPU |
a11e0696 IL |
154 | { |
155 | "FPU test", | |
156 | "fpu", | |
157 | "This test verifies the arithmetic logic unit of" | |
158 | " FPU.", | |
159 | POST_RAM | POST_ALWAYS, | |
160 | &fpu_post_test, | |
161 | NULL, | |
162 | NULL, | |
6d0f6bcf | 163 | CONFIG_SYS_POST_FPU |
a11e0696 IL |
164 | }, |
165 | #endif | |
6d0f6bcf | 166 | #if CONFIG_POST & CONFIG_SYS_POST_UART |
324f6cfd | 167 | { |
8bde7f77 WD |
168 | "UART test", |
169 | "uart", | |
170 | "This test verifies the UART operation.", | |
8564acf9 | 171 | POST_RAM | POST_SLOWTEST | POST_MANUAL, |
8bde7f77 WD |
172 | &uart_post_test, |
173 | NULL, | |
174 | NULL, | |
6d0f6bcf | 175 | CONFIG_SYS_POST_UART |
324f6cfd WD |
176 | }, |
177 | #endif | |
6d0f6bcf | 178 | #if CONFIG_POST & CONFIG_SYS_POST_ETHER |
324f6cfd | 179 | { |
8bde7f77 WD |
180 | "ETHERNET test", |
181 | "ethernet", | |
182 | "This test verifies the ETHERNET operation.", | |
183 | POST_RAM | POST_ALWAYS | POST_MANUAL, | |
184 | ðer_post_test, | |
185 | NULL, | |
186 | NULL, | |
6d0f6bcf | 187 | CONFIG_SYS_POST_ETHER |
324f6cfd WD |
188 | }, |
189 | #endif | |
6d0f6bcf | 190 | #if CONFIG_POST & CONFIG_SYS_POST_SPI |
324f6cfd | 191 | { |
8bde7f77 WD |
192 | "SPI test", |
193 | "spi", | |
194 | "This test verifies the SPI operation.", | |
195 | POST_RAM | POST_ALWAYS | POST_MANUAL, | |
196 | &spi_post_test, | |
197 | NULL, | |
198 | NULL, | |
6d0f6bcf | 199 | CONFIG_SYS_POST_SPI |
324f6cfd WD |
200 | }, |
201 | #endif | |
6d0f6bcf | 202 | #if CONFIG_POST & CONFIG_SYS_POST_USB |
324f6cfd | 203 | { |
8bde7f77 WD |
204 | "USB test", |
205 | "usb", | |
206 | "This test verifies the USB operation.", | |
207 | POST_RAM | POST_ALWAYS | POST_MANUAL, | |
208 | &usb_post_test, | |
209 | NULL, | |
210 | NULL, | |
6d0f6bcf | 211 | CONFIG_SYS_POST_USB |
324f6cfd WD |
212 | }, |
213 | #endif | |
6d0f6bcf | 214 | #if CONFIG_POST & CONFIG_SYS_POST_SPR |
324f6cfd | 215 | { |
8bde7f77 WD |
216 | "SPR test", |
217 | "spr", | |
218 | "This test checks SPR contents.", | |
b2e2142c | 219 | POST_RAM | POST_ALWAYS, |
8bde7f77 WD |
220 | &spr_post_test, |
221 | NULL, | |
222 | NULL, | |
6d0f6bcf | 223 | CONFIG_SYS_POST_SPR |
324f6cfd WD |
224 | }, |
225 | #endif | |
6d0f6bcf | 226 | #if CONFIG_POST & CONFIG_SYS_POST_SYSMON |
4532cb69 | 227 | { |
8bde7f77 WD |
228 | "SYSMON test", |
229 | "sysmon", | |
230 | "This test monitors system hardware.", | |
231 | POST_RAM | POST_ALWAYS, | |
232 | &sysmon_post_test, | |
233 | &sysmon_init_f, | |
234 | &sysmon_reloc, | |
6d0f6bcf | 235 | CONFIG_SYS_POST_SYSMON |
4532cb69 WD |
236 | }, |
237 | #endif | |
6d0f6bcf | 238 | #if CONFIG_POST & CONFIG_SYS_POST_DSP |
5a8c51cd WD |
239 | { |
240 | "DSP test", | |
241 | "dsp", | |
242 | "This test checks any connected DSP(s).", | |
5744ddc6 | 243 | POST_RAM | POST_ALWAYS | POST_MANUAL, |
5a8c51cd WD |
244 | &dsp_post_test, |
245 | NULL, | |
246 | NULL, | |
6d0f6bcf | 247 | CONFIG_SYS_POST_DSP |
5a8c51cd WD |
248 | }, |
249 | #endif | |
6d0f6bcf | 250 | #if CONFIG_POST & CONFIG_SYS_POST_CODEC |
79fa88f3 WD |
251 | { |
252 | "CODEC test", | |
253 | "codec", | |
254 | "This test checks any connected codec(s).", | |
255 | POST_RAM | POST_MANUAL, | |
256 | &codec_post_test, | |
257 | NULL, | |
258 | NULL, | |
6d0f6bcf | 259 | CONFIG_SYS_POST_CODEC |
79fa88f3 WD |
260 | }, |
261 | #endif | |
6d0f6bcf | 262 | #if CONFIG_POST & CONFIG_SYS_POST_ECC |
531e3e8b PK |
263 | { |
264 | "ECC test", | |
265 | "ecc", | |
8dafa874 LJ |
266 | "This test checks the ECC facility of memory.", |
267 | POST_ROM | POST_ALWAYS | POST_PREREL, | |
531e3e8b PK |
268 | &ecc_post_test, |
269 | NULL, | |
270 | NULL, | |
6d0f6bcf | 271 | CONFIG_SYS_POST_ECC |
531e3e8b PK |
272 | }, |
273 | #endif | |
6d0f6bcf | 274 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 |
65b20dce YT |
275 | CONFIG_POST_BSPEC1, |
276 | #endif | |
6d0f6bcf | 277 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 |
65b20dce YT |
278 | CONFIG_POST_BSPEC2, |
279 | #endif | |
6d0f6bcf | 280 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 |
65b20dce YT |
281 | CONFIG_POST_BSPEC3, |
282 | #endif | |
6d0f6bcf | 283 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 |
65b20dce YT |
284 | CONFIG_POST_BSPEC4, |
285 | #endif | |
6d0f6bcf | 286 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC5 |
65b20dce YT |
287 | CONFIG_POST_BSPEC5, |
288 | #endif | |
324f6cfd WD |
289 | }; |
290 | ||
291 | unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test); |