[people/ms/u-boot.git] / tools / ifdtool.h

/*
 * ifdtool - Manage Intel Firmware Descriptor information
 *
 * Copyright (C) 2011 The ChromiumOS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0
 *
 * From Coreboot project
 */

#include <stdint.h>

#define __packed	__attribute__((packed))

#define IFDTOOL_VERSION "1.1-U-Boot"

#define WRITE_MAX	16

enum spi_frequency {
	SPI_FREQUENCY_20MHZ = 0,
	SPI_FREQUENCY_33MHZ = 1,
	SPI_FREQUENCY_50MHZ = 4,
};

enum component_density {
	COMPONENT_DENSITY_512KB = 0,
	COMPONENT_DENSITY_1MB   = 1,
	COMPONENT_DENSITY_2MB   = 2,
	COMPONENT_DENSITY_4MB   = 3,
	COMPONENT_DENSITY_8MB   = 4,
	COMPONENT_DENSITY_16MB  = 5,
};

/* flash descriptor */
struct __packed fdbar_t {
	uint32_t flvalsig;
	uint32_t flmap0;
	uint32_t flmap1;
	uint32_t flmap2;
	uint8_t  reserved[0xefc - 0x20];
	uint32_t flumap1;
};

#define MAX_REGIONS	5

/* regions */
struct __packed frba_t {
	uint32_t flreg[MAX_REGIONS];
};

/* component section */
struct __packed fcba_t {
	uint32_t flcomp;
	uint32_t flill;
	uint32_t flpb;
};

#define MAX_STRAPS	18

/* pch strap */
struct __packed fpsba_t {
	uint32_t pchstrp[MAX_STRAPS];
};

/* master */
struct __packed fmba_t {
	uint32_t flmstr1;
	uint32_t flmstr2;
	uint32_t flmstr3;
};

/* processor strap */
struct __packed fmsba_t {
	uint32_t data[8];
};

/* ME VSCC */
struct vscc_t {
	uint32_t jid;
	uint32_t vscc;
};

struct vtba_t {
	/* Actual number of entries specified in vtl */
	struct vscc_t entry[8];
};

struct region_t {
	int base, limit, size;
};
Commit	Line	Data
cd392fe8 SG	1	/*
	2	* ifdtool - Manage Intel Firmware Descriptor information
	3	*
	4	* Copyright (C) 2011 The ChromiumOS Authors.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0
	7	*
	8	* From Coreboot project
	9	*/
	10
	11	#include <stdint.h>
	12
	13	#define __packed __attribute__((packed))
	14
	15	#define IFDTOOL_VERSION "1.1-U-Boot"
	16
673ed2f8 BM	17	#define WRITE_MAX 16
673ed2f8 BM	18
cd392fe8 SG	19	enum spi_frequency {
	20	SPI_FREQUENCY_20MHZ = 0,
	21	SPI_FREQUENCY_33MHZ = 1,
	22	SPI_FREQUENCY_50MHZ = 4,
	23	};
	24
	25	enum component_density {
	26	COMPONENT_DENSITY_512KB = 0,
	27	COMPONENT_DENSITY_1MB = 1,
	28	COMPONENT_DENSITY_2MB = 2,
	29	COMPONENT_DENSITY_4MB = 3,
	30	COMPONENT_DENSITY_8MB = 4,
	31	COMPONENT_DENSITY_16MB = 5,
	32	};
	33
	34	/* flash descriptor */
	35	struct __packed fdbar_t {
	36	uint32_t flvalsig;
	37	uint32_t flmap0;
	38	uint32_t flmap1;
	39	uint32_t flmap2;
	40	uint8_t reserved[0xefc - 0x20];
	41	uint32_t flumap1;
	42	};
	43
	44	#define MAX_REGIONS 5
	45
	46	/* regions */
	47	struct __packed frba_t {
	48	uint32_t flreg[MAX_REGIONS];
	49	};
	50
	51	/* component section */
	52	struct __packed fcba_t {
	53	uint32_t flcomp;
	54	uint32_t flill;
	55	uint32_t flpb;
	56	};
	57
	58	#define MAX_STRAPS 18
	59
	60	/* pch strap */
	61	struct __packed fpsba_t {
	62	uint32_t pchstrp[MAX_STRAPS];
	63	};
	64
	65	/* master */
	66	struct __packed fmba_t {
	67	uint32_t flmstr1;
	68	uint32_t flmstr2;
	69	uint32_t flmstr3;
	70	};
	71
	72	/* processor strap */
	73	struct __packed fmsba_t {
	74	uint32_t data[8];
	75	};
	76
	77	/* ME VSCC */
	78	struct vscc_t {
	79	uint32_t jid;
	80	uint32_t vscc;
	81	};
	82
83	struct vtba_t {
84	/* Actual number of entries specified in vtl */
85	struct vscc_t entry[8];
86	};
87
88	struct region_t {
89	int base, limit, size;
90	};