arch/arm/cpu/arm1136/cpu.c

   1 /*
   2  * (C) Copyright 2004 Texas Insturments
   3  *
   4  * (C) Copyright 2002
   5  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * (C) Copyright 2002
   9  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /*
  15  * CPU specific code
  16  */
  17
  18 #include <common.h>
  19 #include <command.h>
  20 #include <asm/system.h>
  21
  22 static void cache_flush(void);
  23
  24 int cleanup_before_linux (void)
  25 {
  26         /*
  27          * this function is called just before we call linux
  28          * it prepares the processor for linux
  29          *
  30          * we turn off caches etc ...
  31          */
  32
  33         disable_interrupts ();
  34
  35 #ifdef CONFIG_LCD
  36         {
  37                 extern void lcd_disable(void);
  38                 extern void lcd_panel_disable(void);
  39
  40                 lcd_disable(); /* proper disable of lcd & panel */
  41                 lcd_panel_disable();
  42         }
  43 #endif
  44
  45         /* turn off I/D-cache */
  46         icache_disable();
  47         dcache_disable();
  48         /* flush I/D-cache */
  49         cache_flush();
  50
  51         return 0;
  52 }
  53
  54 static void cache_flush(void)
  55 {
  56         unsigned long i = 0;
  57         /* clean entire data cache */
  58         asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
  59         /* invalidate both caches and flush btb */
  60         asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
  61         /* mem barrier to sync things */
  62         asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
  63 }
  64
  65 #ifndef CONFIG_SYS_DCACHE_OFF
  66
  67 #ifndef CONFIG_SYS_CACHELINE_SIZE
  68 #define CONFIG_SYS_CACHELINE_SIZE       32
  69 #endif
  70
  71 void invalidate_dcache_all(void)
  72 {
  73         asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
  74 }
  75
  76 void flush_dcache_all(void)
  77 {
  78         asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
  79         asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  80 }
  81
  82 static int check_cache_range(unsigned long start, unsigned long stop)
  83 {
  84         int ok = 1;
  85
  86         if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
  87                 ok = 0;
  88
  89         if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
  90                 ok = 0;
  91
  92         if (!ok)
  93                 debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
  94                         start, stop);
  95
  96         return ok;
  97 }
  98
  99 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 100 {
 101         if (!check_cache_range(start, stop))
 102                 return;
 103
 104         while (start < stop) {
 105                 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
 106                 start += CONFIG_SYS_CACHELINE_SIZE;
 107         }
 108 }
 109
 110 void flush_dcache_range(unsigned long start, unsigned long stop)
 111 {
 112         if (!check_cache_range(start, stop))
 113                 return;
 114
 115         while (start < stop) {
 116                 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
 117                 start += CONFIG_SYS_CACHELINE_SIZE;
 118         }
 119
 120         asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 121 }
 122
 123 void flush_cache(unsigned long start, unsigned long size)
 124 {
 125         flush_dcache_range(start, start + size);
 126 }
 127
 128 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 129 void invalidate_dcache_all(void)
 130 {
 131 }
 132
 133 void flush_dcache_all(void)
 134 {
 135 }
 136
 137 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 138 {
 139 }
 140
 141 void flush_dcache_range(unsigned long start, unsigned long stop)
 142 {
 143 }
 144
 145 void flush_cache(unsigned long start, unsigned long size)
 146 {
 147 }
 148 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 149
 150 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
 151 void enable_caches(void)
 152 {
 153 #ifndef CONFIG_SYS_ICACHE_OFF
 154         icache_enable();
 155 #endif
 156 #ifndef CONFIG_SYS_DCACHE_OFF
 157         dcache_enable();
 158 #endif
 159 }
 160 #endif