arch/arm/cpu/arm1136/start.S

   1 /*
   2  *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
   3  *
   4  *  Copyright (c) 2004  Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   7  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   8  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
   9  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  10  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <asm-offsets.h>
  32 #include <config.h>
  33 #include <version.h>
  34 .globl _start
  35 _start: b       reset
  36 #ifdef CONFIG_SPL_BUILD
  37         ldr     pc, _hang
  38         ldr     pc, _hang
  39         ldr     pc, _hang
  40         ldr     pc, _hang
  41         ldr     pc, _hang
  42         ldr     pc, _hang
  43         ldr     pc, _hang
  44
  45 _hang:
  46         .word   do_hang
  47         .word   0x12345678
  48         .word   0x12345678
  49         .word   0x12345678
  50         .word   0x12345678
  51         .word   0x12345678
  52         .word   0x12345678
  53         .word   0x12345678      /* now 16*4=64 */
  54 #else
  55         ldr     pc, _undefined_instruction
  56         ldr     pc, _software_interrupt
  57         ldr     pc, _prefetch_abort
  58         ldr     pc, _data_abort
  59         ldr     pc, _not_used
  60         ldr     pc, _irq
  61         ldr     pc, _fiq
  62
  63 _undefined_instruction: .word undefined_instruction
  64 _software_interrupt:    .word software_interrupt
  65 _prefetch_abort:        .word prefetch_abort
  66 _data_abort:            .word data_abort
  67 _not_used:              .word not_used
  68 _irq:                   .word irq
  69 _fiq:                   .word fiq
  70 _pad:                   .word 0x12345678 /* now 16*4=64 */
  71 #endif  /* CONFIG_SPL_BUILD */
  72 .global _end_vect
  73 _end_vect:
  74
  75         .balignl 16,0xdeadbeef
  76 /*
  77  *************************************************************************
  78  *
  79  * Startup Code (reset vector)
  80  *
  81  * do important init only if we don't start from memory!
  82  * setup Memory and board specific bits prior to relocation.
  83  * relocate armboot to ram
  84  * setup stack
  85  *
  86  *************************************************************************
  87  */
  88
  89 .globl _TEXT_BASE
  90 _TEXT_BASE:
  91 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  92         .word   CONFIG_SPL_TEXT_BASE
  93 #else
  94         .word   CONFIG_SYS_TEXT_BASE
  95 #endif
  96
  97 /*
  98  * These are defined in the board-specific linker script.
  99  * Subtracting _start from them lets the linker put their
 100  * relative position in the executable instead of leaving
 101  * them null.
 102  */
 103 .globl _bss_start_ofs
 104 _bss_start_ofs:
 105         .word __bss_start - _start
 106
 107 .globl _image_copy_end_ofs
 108 _image_copy_end_ofs:
 109         .word __image_copy_end - _start
 110
 111 .globl _bss_end_ofs
 112 _bss_end_ofs:
 113         .word __bss_end - _start
 114
 115 .globl _end_ofs
 116 _end_ofs:
 117         .word _end - _start
 118
 119 #ifdef CONFIG_USE_IRQ
 120 /* IRQ stack memory (calculated at run-time) */
 121 .globl IRQ_STACK_START
 122 IRQ_STACK_START:
 123         .word   0x0badc0de
 124
 125 /* IRQ stack memory (calculated at run-time) */
 126 .globl FIQ_STACK_START
 127 FIQ_STACK_START:
 128         .word 0x0badc0de
 129 #endif
 130
 131 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 132 .globl IRQ_STACK_START_IN
 133 IRQ_STACK_START_IN:
 134         .word   0x0badc0de
 135
 136 /*
 137  * the actual reset code
 138  */
 139
 140 reset:
 141         /*
 142          * set the cpu to SVC32 mode
 143          */
 144         mrs     r0,cpsr
 145         bic     r0,r0,#0x1f
 146         orr     r0,r0,#0xd3
 147         msr     cpsr,r0
 148
 149 #ifdef CONFIG_OMAP2420H4
 150        /* Copy vectors to mask ROM indirect addr */
 151         adr     r0, _start              /* r0 <- current position of code   */
 152                 add     r0, r0, #4                              /* skip reset vector                    */
 153         mov     r2, #64                 /* r2 <- size to copy  */
 154         add     r2, r0, r2              /* r2 <- source end address         */
 155         mov     r1, #SRAM_OFFSET0         /* build vect addr */
 156         mov     r3, #SRAM_OFFSET1
 157         add     r1, r1, r3
 158         mov     r3, #SRAM_OFFSET2
 159         add     r1, r1, r3
 160 next:
 161         ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 162         stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 163         cmp     r0, r2                  /* until source end address [r2]    */
 164         bne     next                    /* loop until equal */
 165         bl      cpy_clk_code            /* put dpll adjust code behind vectors */
 166 #endif
 167         /* the mask ROM code should have PLL and others stable */
 168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 169         bl  cpu_init_crit
 170 #endif
 171
 172         bl      _main
 173
 174 /*------------------------------------------------------------------------------*/
 175
 176 /*
 177  * void relocate_code(addr_moni)
 178  *
 179  * This function relocates the monitor code.
 180  */
 181         .globl  relocate_code
 182 relocate_code:
 183         mov     r6, r0  /* save addr of destination */
 184
 185         adr     r0, _start
 186         subs    r9, r6, r0              /* r9 <- relocation offset */
 187         beq     relocate_done           /* skip relocation */
 188         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 189         ldr     r3, _image_copy_end_ofs
 190         add     r2, r0, r3              /* r2 <- source end address         */
 191
 192 copy_loop:
 193         ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
 194         stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
 195         cmp     r0, r2                  /* until source end address [r2]    */
 196         blo     copy_loop
 197
 198 #ifndef CONFIG_SPL_BUILD
 199         /*
 200          * fix .rel.dyn relocations
 201          */
 202         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 203         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 204         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 205         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 206         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 207         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 208         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 209 fixloop:
 210         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 211         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 212         ldr     r1, [r2, #4]
 213         and     r7, r1, #0xff
 214         cmp     r7, #23                 /* relative fixup? */
 215         beq     fixrel
 216         cmp     r7, #2                  /* absolute fixup? */
 217         beq     fixabs
 218         /* ignore unknown type of fixup */
 219         b       fixnext
 220 fixabs:
 221         /* absolute fix: set location to (offset) symbol value */
 222         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 223         add     r1, r10, r1             /* r1 <- address of symbol in table */
 224         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 225         add     r1, r1, r9              /* r1 <- relocated sym addr */
 226         b       fixnext
 227 fixrel:
 228         /* relative fix: increase location by offset */
 229         ldr     r1, [r0]
 230         add     r1, r1, r9
 231 fixnext:
 232         str     r1, [r0]
 233         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 234         cmp     r2, r3
 235         blo     fixloop
 236 #endif
 237
 238 relocate_done:
 239
 240         bx      lr
 241
 242 #ifndef CONFIG_SPL_BUILD
 243
 244 _rel_dyn_start_ofs:
 245         .word __rel_dyn_start - _start
 246 _rel_dyn_end_ofs:
 247         .word __rel_dyn_end - _start
 248 _dynsym_start_ofs:
 249         .word __dynsym_start - _start
 250
 251 #endif
 252
 253         .globl  c_runtime_cpu_setup
 254 c_runtime_cpu_setup:
 255
 256         bx      lr
 257
 258 /*
 259  *************************************************************************
 260  *
 261  * CPU_init_critical registers
 262  *
 263  * setup important registers
 264  * setup memory timing
 265  *
 266  *************************************************************************
 267  */
 268 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 269 cpu_init_crit:
 270         /*
 271          * flush v4 I/D caches
 272          */
 273         mov     r0, #0
 274         mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I+D+BTB caches */
 275         mcr     p15, 0, r0, c8, c7, 0   /* Invalidate Unified TLB */
 276
 277         /*
 278          * disable MMU stuff and caches
 279          */
 280         mrc     p15, 0, r0, c1, c0, 0
 281         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 282         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 283         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 284         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 285         mcr     p15, 0, r0, c1, c0, 0
 286
 287         /*
 288          * Jump to board specific initialization... The Mask ROM will have already initialized
 289          * basic memory.  Go here to bump up clock rate and handle wake up conditions.
 290          */
 291         mov     ip, lr          /* persevere link reg across call */
 292         bl      lowlevel_init   /* go setup pll,mux,memory */
 293         mov     lr, ip          /* restore link */
 294         mov     pc, lr          /* back to my caller */
 295 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 296
 297 #ifndef CONFIG_SPL_BUILD
 298 /*
 299  *************************************************************************
 300  *
 301  * Interrupt handling
 302  *
 303  *************************************************************************
 304  */
 305 @
 306 @ IRQ stack frame.
 307 @
 308 #define S_FRAME_SIZE    72
 309
 310 #define S_OLD_R0        68
 311 #define S_PSR           64
 312 #define S_PC            60
 313 #define S_LR            56
 314 #define S_SP            52
 315
 316 #define S_IP            48
 317 #define S_FP            44
 318 #define S_R10           40
 319 #define S_R9            36
 320 #define S_R8            32
 321 #define S_R7            28
 322 #define S_R6            24
 323 #define S_R5            20
 324 #define S_R4            16
 325 #define S_R3            12
 326 #define S_R2            8
 327 #define S_R1            4
 328 #define S_R0            0
 329
 330 #define MODE_SVC 0x13
 331 #define I_BIT    0x80
 332
 333 /*
 334  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 335  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 336  */
 337
 338         .macro  bad_save_user_regs
 339         sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 340         stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 341
 342         ldr     r2, IRQ_STACK_START_IN          @ set base 2 words into abort stack
 343         ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 344         add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 345
 346         add     r5, sp, #S_SP
 347         mov     r1, lr
 348         stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 349         mov     r0, sp                          @ save current stack into r0 (param register)
 350         .endm
 351
 352         .macro  irq_save_user_regs
 353         sub     sp, sp, #S_FRAME_SIZE
 354         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 355         add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 356         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 357         str     lr, [r8, #0]                    @ Save calling PC
 358         mrs     r6, spsr
 359         str     r6, [r8, #4]                    @ Save CPSR
 360         str     r0, [r8, #8]                    @ Save OLD_R0
 361         mov     r0, sp
 362         .endm
 363
 364         .macro  irq_restore_user_regs
 365         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 366         mov     r0, r0
 367         ldr     lr, [sp, #S_PC]                 @ Get PC
 368         add     sp, sp, #S_FRAME_SIZE
 369         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 370         .endm
 371
 372         .macro get_bad_stack
 373         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack (enter in banked mode)
 374
 375         str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 376         mrs     lr, spsr                        @ get the spsr
 377         str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 378
 379         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 380         @ msr   spsr_c, r13
 381         msr     spsr, r13                       @ switch modes, make sure moves will execute
 382         mov     lr, pc                          @ capture return pc
 383         movs    pc, lr                          @ jump to next instruction & switch modes.
 384         .endm
 385
 386         .macro get_bad_stack_swi
 387         sub     r13, r13, #4                    @ space on current stack for scratch reg.
 388         str     r0, [r13]                       @ save R0's value.
 389         ldr     r0, IRQ_STACK_START_IN          @ get data regions start
 390         str     lr, [r0]                        @ save caller lr in position 0 of saved stack
 391         mrs     r0, spsr                        @ get the spsr
 392         str     lr, [r0, #4]                    @ save spsr in position 1 of saved stack
 393         ldr     r0, [r13]                       @ restore r0
 394         add     r13, r13, #4                    @ pop stack entry
 395         .endm
 396
 397         .macro get_irq_stack                    @ setup IRQ stack
 398         ldr     sp, IRQ_STACK_START
 399         .endm
 400
 401         .macro get_fiq_stack                    @ setup FIQ stack
 402         ldr     sp, FIQ_STACK_START
 403         .endm
 404 #endif  /* CONFIG_SPL_BUILD */
 405
 406 /*
 407  * exception handlers
 408  */
 409 #ifdef CONFIG_SPL_BUILD
 410         .align  5
 411 do_hang:
 412         ldr     sp, _TEXT_BASE                  /* use 32 words about stack */
 413         bl      hang                            /* hang and never return */
 414 #else   /* !CONFIG_SPL_BUILD */
 415         .align  5
 416 undefined_instruction:
 417         get_bad_stack
 418         bad_save_user_regs
 419         bl      do_undefined_instruction
 420
 421         .align  5
 422 software_interrupt:
 423         get_bad_stack_swi
 424         bad_save_user_regs
 425         bl      do_software_interrupt
 426
 427         .align  5
 428 prefetch_abort:
 429         get_bad_stack
 430         bad_save_user_regs
 431         bl      do_prefetch_abort
 432
 433         .align  5
 434 data_abort:
 435         get_bad_stack
 436         bad_save_user_regs
 437         bl      do_data_abort
 438
 439         .align  5
 440 not_used:
 441         get_bad_stack
 442         bad_save_user_regs
 443         bl      do_not_used
 444
 445 #ifdef CONFIG_USE_IRQ
 446
 447         .align  5
 448 irq:
 449         get_irq_stack
 450         irq_save_user_regs
 451         bl      do_irq
 452         irq_restore_user_regs
 453
 454         .align  5
 455 fiq:
 456         get_fiq_stack
 457         /* someone ought to write a more effiction fiq_save_user_regs */
 458         irq_save_user_regs
 459         bl      do_fiq
 460         irq_restore_user_regs
 461
 462 #else
 463
 464         .align  5
 465 irq:
 466         get_bad_stack
 467         bad_save_user_regs
 468         bl      do_irq
 469
 470         .align  5
 471 fiq:
 472         get_bad_stack
 473         bad_save_user_regs
 474         bl      do_fiq
 475
 476 #endif
 477         .align 5
 478 .global arm1136_cache_flush
 479 arm1136_cache_flush:
 480 #if !defined(CONFIG_SYS_ICACHE_OFF)
 481                 mcr     p15, 0, r1, c7, c5, 0   @ invalidate I cache
 482 #endif
 483 #if !defined(CONFIG_SYS_DCACHE_OFF)
 484                 mcr     p15, 0, r1, c7, c14, 0  @ invalidate D cache
 485 #endif
 486                 mov     pc, lr                  @ back to caller
 487 #endif  /* CONFIG_SPL_BUILD */