arch/arm/cpu/arm1176/start.S

   1 /*
   2  *  armboot - Startup Code for ARM1176 CPU-core
   3  *
   4  * Copyright (c) 2007   Samsung Electronics
   5  *
   6  * Copyright (C) 2008
   7  * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  *
  11  * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  12  * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  13  * jsgood (jsgood.yang@samsung.com)
  14  * Base codes by scsuh (sc.suh)
  15  */
  16
  17 #include <asm-offsets.h>
  18 #include <config.h>
  19 #include <version.h>
  20
  21 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
  22 #define CONFIG_SYS_PHY_UBOOT_BASE       CONFIG_SYS_UBOOT_BASE
  23 #endif
  24
  25 /*
  26  *************************************************************************
  27  *
  28  * Jump vector table as in table 3.1 in [1]
  29  *
  30  *************************************************************************
  31  */
  32
  33 .globl _start
  34 _start: b       reset
  35 #ifndef CONFIG_SPL_BUILD
  36         ldr     pc, _undefined_instruction
  37         ldr     pc, _software_interrupt
  38         ldr     pc, _prefetch_abort
  39         ldr     pc, _data_abort
  40         ldr     pc, _not_used
  41         ldr     pc, _irq
  42         ldr     pc, _fiq
  43
  44 _undefined_instruction:
  45         .word undefined_instruction
  46 _software_interrupt:
  47         .word software_interrupt
  48 _prefetch_abort:
  49         .word prefetch_abort
  50 _data_abort:
  51         .word data_abort
  52 _not_used:
  53         .word not_used
  54 _irq:
  55         .word irq
  56 _fiq:
  57         .word fiq
  58 _pad:
  59         .word 0x12345678 /* now 16*4=64 */
  60 #else
  61         . = _start + 64
  62 #endif
  63
  64 .global _end_vect
  65 _end_vect:
  66         .balignl 16,0xdeadbeef
  67 /*
  68  *************************************************************************
  69  *
  70  * Startup Code (reset vector)
  71  *
  72  * do important init only if we don't start from memory!
  73  * setup Memory and board specific bits prior to relocation.
  74  * relocate armboot to ram
  75  * setup stack
  76  *
  77  *************************************************************************
  78  */
  79
  80 /* IRQ stack memory (calculated at run-time) + 8 bytes */
  81 .globl IRQ_STACK_START_IN
  82 IRQ_STACK_START_IN:
  83         .word   0x0badc0de
  84
  85 /*
  86  * the actual reset code
  87  */
  88
  89 reset:
  90         /*
  91          * set the cpu to SVC32 mode
  92          */
  93         mrs     r0, cpsr
  94         bic     r0, r0, #0x3f
  95         orr     r0, r0, #0xd3
  96         msr     cpsr, r0
  97
  98 /*
  99  *************************************************************************
 100  *
 101  * CPU_init_critical registers
 102  *
 103  * setup important registers
 104  * setup memory timing
 105  *
 106  *************************************************************************
 107  */
 108         /*
 109          * we do sys-critical inits only at reboot,
 110          * not when booting from ram!
 111          */
 112 cpu_init_crit:
 113         /*
 114          * When booting from NAND - it has definitely been a reset, so, no need
 115          * to flush caches and disable the MMU
 116          */
 117 #ifndef CONFIG_SPL_BUILD
 118         /*
 119          * flush v4 I/D caches
 120          */
 121         mov     r0, #0
 122         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 123         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 124
 125         /*
 126          * disable MMU stuff and caches
 127          */
 128         mrc     p15, 0, r0, c1, c0, 0
 129         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 130         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 131         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 132         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 133
 134         /* Prepare to disable the MMU */
 135         adr     r2, mmu_disable_phys
 136         sub     r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
 137         b       mmu_disable
 138
 139         .align 5
 140         /* Run in a single cache-line */
 141 mmu_disable:
 142         mcr     p15, 0, r0, c1, c0, 0
 143         nop
 144         nop
 145         mov     pc, r2
 146 mmu_disable_phys:
 147
 148 #ifdef CONFIG_DISABLE_TCM
 149         /*
 150          * Disable the TCMs
 151          */
 152         mrc     p15, 0, r0, c0, c0, 2   /* Return TCM details */
 153         cmp     r0, #0
 154         beq     skip_tcmdisable
 155         mov     r1, #0
 156         mov     r2, #1
 157         tst     r0, r2
 158         mcrne   p15, 0, r1, c9, c1, 1   /* Disable Instruction TCM if present*/
 159         tst     r0, r2, LSL #16
 160         mcrne   p15, 0, r1, c9, c1, 0   /* Disable Data TCM if present*/
 161 skip_tcmdisable:
 162 #endif
 163 #endif
 164
 165 #ifdef CONFIG_PERIPORT_REMAP
 166         /* Peri port setup */
 167         ldr     r0, =CONFIG_PERIPORT_BASE
 168         orr     r0, r0, #CONFIG_PERIPORT_SIZE
 169         mcr     p15,0,r0,c15,c2,4
 170 #endif
 171
 172         /*
 173          * Go setup Memory and board specific bits prior to relocation.
 174          */
 175         bl      lowlevel_init           /* go setup pll,mux,memory */
 176
 177         bl      _main
 178
 179 /*------------------------------------------------------------------------------*/
 180
 181         .globl  c_runtime_cpu_setup
 182 c_runtime_cpu_setup:
 183
 184         mov     pc, lr
 185
 186 #ifndef CONFIG_SPL_BUILD
 187 /*
 188  *************************************************************************
 189  *
 190  * Interrupt handling
 191  *
 192  *************************************************************************
 193  */
 194 @
 195 @ IRQ stack frame.
 196 @
 197 #define S_FRAME_SIZE    72
 198
 199 #define S_OLD_R0        68
 200 #define S_PSR           64
 201 #define S_PC            60
 202 #define S_LR            56
 203 #define S_SP            52
 204
 205 #define S_IP            48
 206 #define S_FP            44
 207 #define S_R10           40
 208 #define S_R9            36
 209 #define S_R8            32
 210 #define S_R7            28
 211 #define S_R6            24
 212 #define S_R5            20
 213 #define S_R4            16
 214 #define S_R3            12
 215 #define S_R2            8
 216 #define S_R1            4
 217 #define S_R0            0
 218
 219 #define MODE_SVC 0x13
 220 #define I_BIT    0x80
 221
 222 /*
 223  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 224  */
 225
 226         .macro  bad_save_user_regs
 227         /* carve out a frame on current user stack */
 228         sub     sp, sp, #S_FRAME_SIZE
 229         /* Save user registers (now in svc mode) r0-r12 */
 230         stmia   sp, {r0 - r12}
 231
 232         ldr     r2, IRQ_STACK_START_IN
 233         /* get values for "aborted" pc and cpsr (into parm regs) */
 234         ldmia   r2, {r2 - r3}
 235         /* grab pointer to old stack */
 236         add     r0, sp, #S_FRAME_SIZE
 237
 238         add     r5, sp, #S_SP
 239         mov     r1, lr
 240         /* save sp_SVC, lr_SVC, pc, cpsr */
 241         stmia   r5, {r0 - r3}
 242         /* save current stack into r0 (param register) */
 243         mov     r0, sp
 244         .endm
 245
 246         .macro get_bad_stack
 247         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 248
 249         /* save caller lr in position 0 of saved stack */
 250         str     lr, [r13]
 251         /* get the spsr */
 252         mrs     lr, spsr
 253         /* save spsr in position 1 of saved stack */
 254         str     lr, [r13, #4]
 255
 256         /* prepare SVC-Mode */
 257         mov     r13, #MODE_SVC
 258         @ msr   spsr_c, r13
 259         /* switch modes, make sure moves will execute */
 260         msr     spsr, r13
 261         /* capture return pc */
 262         mov     lr, pc
 263         /* jump to next instruction & switch modes. */
 264         movs    pc, lr
 265         .endm
 266
 267         .macro get_bad_stack_swi
 268         /* space on current stack for scratch reg. */
 269         sub     r13, r13, #4
 270         /* save R0's value. */
 271         str     r0, [r13]
 272         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 273         /* save caller lr in position 0 of saved stack */
 274         str     lr, [r0]
 275         /* get the spsr */
 276         mrs     lr, spsr
 277         /* save spsr in position 1 of saved stack */
 278         str     lr, [r0, #4]
 279         /* restore lr */
 280         ldr     lr, [r0]
 281         /* restore r0 */
 282         ldr     r0, [r13]
 283         /* pop stack entry */
 284         add     r13, r13, #4
 285         .endm
 286
 287 /*
 288  * exception handlers
 289  */
 290         .align  5
 291 undefined_instruction:
 292         get_bad_stack
 293         bad_save_user_regs
 294         bl      do_undefined_instruction
 295
 296         .align  5
 297 software_interrupt:
 298         get_bad_stack_swi
 299         bad_save_user_regs
 300         bl      do_software_interrupt
 301
 302         .align  5
 303 prefetch_abort:
 304         get_bad_stack
 305         bad_save_user_regs
 306         bl      do_prefetch_abort
 307
 308         .align  5
 309 data_abort:
 310         get_bad_stack
 311         bad_save_user_regs
 312         bl      do_data_abort
 313
 314         .align  5
 315 not_used:
 316         get_bad_stack
 317         bad_save_user_regs
 318         bl      do_not_used
 319
 320         .align  5
 321 irq:
 322         get_bad_stack
 323         bad_save_user_regs
 324         bl      do_irq
 325
 326         .align  5
 327 fiq:
 328         get_bad_stack
 329         bad_save_user_regs
 330         bl      do_fiq
 331 #endif /* CONFIG_SPL_BUILD */