arch/arm/cpu/arm1176/start.S

   1 /*
   2  *  armboot - Startup Code for ARM1176 CPU-core
   3  *
   4  * Copyright (c) 2007   Samsung Electronics
   5  *
   6  * Copyright (C) 2008
   7  * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
  28  * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
  29  * jsgood (jsgood.yang@samsung.com)
  30  * Base codes by scsuh (sc.suh)
  31  */
  32
  33 #include <asm-offsets.h>
  34 #include <config.h>
  35 #include <version.h>
  36 #ifdef CONFIG_ENABLE_MMU
  37 #include <asm/proc/domain.h>
  38 #endif
  39
  40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
  41 #define CONFIG_SYS_PHY_UBOOT_BASE       CONFIG_SYS_UBOOT_BASE
  42 #endif
  43
  44 /*
  45  *************************************************************************
  46  *
  47  * Jump vector table as in table 3.1 in [1]
  48  *
  49  *************************************************************************
  50  */
  51
  52 .globl _start
  53 _start: b       reset
  54 #ifndef CONFIG_NAND_SPL
  55         ldr     pc, _undefined_instruction
  56         ldr     pc, _software_interrupt
  57         ldr     pc, _prefetch_abort
  58         ldr     pc, _data_abort
  59         ldr     pc, _not_used
  60         ldr     pc, _irq
  61         ldr     pc, _fiq
  62
  63 _undefined_instruction:
  64         .word undefined_instruction
  65 _software_interrupt:
  66         .word software_interrupt
  67 _prefetch_abort:
  68         .word prefetch_abort
  69 _data_abort:
  70         .word data_abort
  71 _not_used:
  72         .word not_used
  73 _irq:
  74         .word irq
  75 _fiq:
  76         .word fiq
  77 _pad:
  78         .word 0x12345678 /* now 16*4=64 */
  79 #else
  80         . = _start + 64
  81 #endif
  82
  83 .global _end_vect
  84 _end_vect:
  85         .balignl 16,0xdeadbeef
  86 /*
  87  *************************************************************************
  88  *
  89  * Startup Code (reset vector)
  90  *
  91  * do important init only if we don't start from memory!
  92  * setup Memory and board specific bits prior to relocation.
  93  * relocate armboot to ram
  94  * setup stack
  95  *
  96  *************************************************************************
  97  */
  98
  99 .globl _TEXT_BASE
 100 _TEXT_BASE:
 101         .word   CONFIG_SYS_TEXT_BASE
 102
 103 /*
 104  * Below variable is very important because we use MMU in U-Boot.
 105  * Without it, we cannot run code correctly before MMU is ON.
 106  * by scsuh.
 107  */
 108 _TEXT_PHY_BASE:
 109         .word   CONFIG_SYS_PHY_UBOOT_BASE
 110
 111 /*
 112  * These are defined in the board-specific linker script.
 113  * Subtracting _start from them lets the linker put their
 114  * relative position in the executable instead of leaving
 115  * them null.
 116  */
 117
 118 .globl _bss_start_ofs
 119 _bss_start_ofs:
 120         .word __bss_start - _start
 121
 122 .globl _bss_end_ofs
 123 _bss_end_ofs:
 124         .word __bss_end__ - _start
 125
 126 .globl _end_ofs
 127 _end_ofs:
 128         .word _end - _start
 129
 130 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 131 .globl IRQ_STACK_START_IN
 132 IRQ_STACK_START_IN:
 133         .word   0x0badc0de
 134
 135 /*
 136  * the actual reset code
 137  */
 138
 139 reset:
 140         /*
 141          * set the cpu to SVC32 mode
 142          */
 143         mrs     r0, cpsr
 144         bic     r0, r0, #0x3f
 145         orr     r0, r0, #0xd3
 146         msr     cpsr, r0
 147
 148 /*
 149  *************************************************************************
 150  *
 151  * CPU_init_critical registers
 152  *
 153  * setup important registers
 154  * setup memory timing
 155  *
 156  *************************************************************************
 157  */
 158         /*
 159          * we do sys-critical inits only at reboot,
 160          * not when booting from ram!
 161          */
 162 cpu_init_crit:
 163         /*
 164          * When booting from NAND - it has definitely been a reset, so, no need
 165          * to flush caches and disable the MMU
 166          */
 167 #ifndef CONFIG_NAND_SPL
 168         /*
 169          * flush v4 I/D caches
 170          */
 171         mov     r0, #0
 172         mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 173         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 174
 175         /*
 176          * disable MMU stuff and caches
 177          */
 178         mrc     p15, 0, r0, c1, c0, 0
 179         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 180         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 181         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 182         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 183
 184         /* Prepare to disable the MMU */
 185         adr     r2, mmu_disable_phys
 186         sub     r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
 187         b       mmu_disable
 188
 189         .align 5
 190         /* Run in a single cache-line */
 191 mmu_disable:
 192         mcr     p15, 0, r0, c1, c0, 0
 193         nop
 194         nop
 195         mov     pc, r2
 196 mmu_disable_phys:
 197
 198 #ifdef CONFIG_DISABLE_TCM
 199         /*
 200          * Disable the TCMs
 201          */
 202         mrc     p15, 0, r0, c0, c0, 2   /* Return TCM details */
 203         cmp     r0, #0
 204         beq     skip_tcmdisable
 205         mov     r1, #0
 206         mov     r2, #1
 207         tst     r0, r2
 208         mcrne   p15, 0, r1, c9, c1, 1   /* Disable Instruction TCM if present*/
 209         tst     r0, r2, LSL #16
 210         mcrne   p15, 0, r1, c9, c1, 0   /* Disable Data TCM if present*/
 211 skip_tcmdisable:
 212 #endif
 213 #endif
 214
 215 #ifdef CONFIG_PERIPORT_REMAP
 216         /* Peri port setup */
 217         ldr     r0, =CONFIG_PERIPORT_BASE
 218         orr     r0, r0, #CONFIG_PERIPORT_SIZE
 219         mcr     p15,0,r0,c15,c2,4
 220 #endif
 221
 222         /*
 223          * Go setup Memory and board specific bits prior to relocation.
 224          */
 225         bl      lowlevel_init           /* go setup pll,mux,memory */
 226
 227 /* Set stackpointer in internal RAM to call board_init_f */
 228 call_board_init_f:
 229         ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
 230         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 231         ldr     r0,=0x00000000
 232         bl      board_init_f
 233
 234 /*------------------------------------------------------------------------------*/
 235
 236 /*
 237  * void relocate_code (addr_sp, gd, addr_moni)
 238  *
 239  * This "function" does not return, instead it continues in RAM
 240  * after relocating the monitor code.
 241  *
 242  */
 243         .globl  relocate_code
 244 relocate_code:
 245         mov     r4, r0  /* save addr_sp */
 246         mov     r5, r1  /* save addr of gd */
 247         mov     r6, r2  /* save addr of destination */
 248
 249         /* Set up the stack                                                 */
 250 stack_setup:
 251         mov     sp, r4
 252
 253         adr     r0, _start
 254         cmp     r0, r6
 255         beq     clear_bss               /* skip relocation */
 256         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 257         ldr     r3, _bss_start_ofs
 258         add     r2, r0, r3              /* r2 <- source end address         */
 259
 260 copy_loop:
 261         ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
 262         stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
 263         cmp     r0, r2                  /* until source end address [r2]    */
 264         blo     copy_loop
 265
 266 #ifndef CONFIG_SPL_BUILD
 267         /*
 268          * fix .rel.dyn relocations
 269          */
 270         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 271         sub     r9, r6, r0              /* r9 <- relocation offset */
 272         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 273         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 274         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 275         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 276         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 277         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 278 fixloop:
 279         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 280         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 281         ldr     r1, [r2, #4]
 282         and     r7, r1, #0xff
 283         cmp     r7, #23                 /* relative fixup? */
 284         beq     fixrel
 285         cmp     r7, #2                  /* absolute fixup? */
 286         beq     fixabs
 287         /* ignore unknown type of fixup */
 288         b       fixnext
 289 fixabs:
 290         /* absolute fix: set location to (offset) symbol value */
 291         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 292         add     r1, r10, r1             /* r1 <- address of symbol in table */
 293         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 294         add     r1, r1, r9              /* r1 <- relocated sym addr */
 295         b       fixnext
 296 fixrel:
 297         /* relative fix: increase location by offset */
 298         ldr     r1, [r0]
 299         add     r1, r1, r9
 300 fixnext:
 301         str     r1, [r0]
 302         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 303         cmp     r2, r3
 304         blo     fixloop
 305 #endif
 306
 307 #ifdef CONFIG_ENABLE_MMU
 308 enable_mmu:
 309         /* enable domain access */
 310         ldr     r5, =0x0000ffff
 311         mcr     p15, 0, r5, c3, c0, 0   /* load domain access register */
 312
 313         /* Set the TTB register */
 314         ldr     r0, _mmu_table_base
 315         ldr     r1, =CONFIG_SYS_PHY_UBOOT_BASE
 316         ldr     r2, =0xfff00000
 317         bic     r0, r0, r2
 318         orr     r1, r0, r1
 319         mcr     p15, 0, r1, c2, c0, 0
 320
 321         /* Enable the MMU */
 322         mrc     p15, 0, r0, c1, c0, 0
 323         orr     r0, r0, #1              /* Set CR_M to enable MMU */
 324
 325         /* Prepare to enable the MMU */
 326         adr     r1, skip_hw_init
 327         and     r1, r1, #0x3fc
 328         ldr     r2, _TEXT_BASE
 329         ldr     r3, =0xfff00000
 330         and     r2, r2, r3
 331         orr     r2, r2, r1
 332         b       mmu_enable
 333
 334         .align 5
 335         /* Run in a single cache-line */
 336 mmu_enable:
 337
 338         mcr     p15, 0, r0, c1, c0, 0
 339         nop
 340         nop
 341         mov     pc, r2
 342 skip_hw_init:
 343 #endif
 344
 345 clear_bss:
 346 #ifndef CONFIG_SPL_BUILD
 347         ldr     r0, _bss_start_ofs
 348         ldr     r1, _bss_end_ofs
 349         mov     r4, r6                  /* reloc addr */
 350         add     r0, r0, r4
 351         add     r1, r1, r4
 352         mov     r2, #0x00000000         /* clear                            */
 353
 354 clbss_l:cmp     r0, r1                  /* clear loop... */
 355         bhs     clbss_e                 /* if reached end of bss, exit */
 356         str     r2, [r0]
 357         add     r0, r0, #4
 358         b       clbss_l
 359 clbss_e:
 360 #ifndef CONFIG_NAND_SPL
 361         bl coloured_LED_init
 362         bl red_led_on
 363 #endif
 364 #endif
 365
 366 /*
 367  * We are done. Do not return, instead branch to second part of board
 368  * initialization, now running from RAM.
 369  */
 370 #ifdef CONFIG_NAND_SPL
 371         ldr     pc, _nand_boot
 372
 373 _nand_boot: .word nand_boot
 374 #else
 375         ldr     r0, _board_init_r_ofs
 376         adr     r1, _start
 377         add     lr, r0, r1
 378         add     lr, lr, r9
 379         /* setup parameters for board_init_r */
 380         mov     r0, r5          /* gd_t */
 381         mov     r1, r6          /* dest_addr */
 382         /* jump to it ... */
 383         mov     pc, lr
 384
 385 _board_init_r_ofs:
 386         .word board_init_r - _start
 387 #endif
 388
 389 _rel_dyn_start_ofs:
 390         .word __rel_dyn_start - _start
 391 _rel_dyn_end_ofs:
 392         .word __rel_dyn_end - _start
 393 _dynsym_start_ofs:
 394         .word __dynsym_start - _start
 395
 396 #ifdef CONFIG_ENABLE_MMU
 397 _mmu_table_base:
 398         .word mmu_table
 399 #endif
 400
 401 #ifndef CONFIG_NAND_SPL
 402 /*
 403  * we assume that cache operation is done before. (eg. cleanup_before_linux())
 404  * actually, we don't need to do anything about cache if not use d-cache in
 405  * U-Boot. So, in this function we clean only MMU. by scsuh
 406  *
 407  * void theLastJump(void *kernel, int arch_num, uint boot_params);
 408  */
 409 #ifdef CONFIG_ENABLE_MMU
 410         .globl theLastJump
 411 theLastJump:
 412         mov     r9, r0
 413         ldr     r3, =0xfff00000
 414         ldr     r4, _TEXT_PHY_BASE
 415         adr     r5, phy_last_jump
 416         bic     r5, r5, r3
 417         orr     r5, r5, r4
 418         mov     pc, r5
 419 phy_last_jump:
 420         /*
 421          * disable MMU stuff
 422          */
 423         mrc     p15, 0, r0, c1, c0, 0
 424         bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
 425         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
 426         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 427         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 428         mcr     p15, 0, r0, c1, c0, 0
 429
 430         mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 431
 432         mov     r0, #0
 433         mov     pc, r9
 434 #endif
 435
 436
 437 /*
 438  *************************************************************************
 439  *
 440  * Interrupt handling
 441  *
 442  *************************************************************************
 443  */
 444 @
 445 @ IRQ stack frame.
 446 @
 447 #define S_FRAME_SIZE    72
 448
 449 #define S_OLD_R0        68
 450 #define S_PSR           64
 451 #define S_PC            60
 452 #define S_LR            56
 453 #define S_SP            52
 454
 455 #define S_IP            48
 456 #define S_FP            44
 457 #define S_R10           40
 458 #define S_R9            36
 459 #define S_R8            32
 460 #define S_R7            28
 461 #define S_R6            24
 462 #define S_R5            20
 463 #define S_R4            16
 464 #define S_R3            12
 465 #define S_R2            8
 466 #define S_R1            4
 467 #define S_R0            0
 468
 469 #define MODE_SVC 0x13
 470 #define I_BIT    0x80
 471
 472 /*
 473  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 474  */
 475
 476         .macro  bad_save_user_regs
 477         /* carve out a frame on current user stack */
 478         sub     sp, sp, #S_FRAME_SIZE
 479         /* Save user registers (now in svc mode) r0-r12 */
 480         stmia   sp, {r0 - r12}
 481
 482         ldr     r2, IRQ_STACK_START_IN
 483         /* get values for "aborted" pc and cpsr (into parm regs) */
 484         ldmia   r2, {r2 - r3}
 485         /* grab pointer to old stack */
 486         add     r0, sp, #S_FRAME_SIZE
 487
 488         add     r5, sp, #S_SP
 489         mov     r1, lr
 490         /* save sp_SVC, lr_SVC, pc, cpsr */
 491         stmia   r5, {r0 - r3}
 492         /* save current stack into r0 (param register) */
 493         mov     r0, sp
 494         .endm
 495
 496         .macro get_bad_stack
 497         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 498
 499         /* save caller lr in position 0 of saved stack */
 500         str     lr, [r13]
 501         /* get the spsr */
 502         mrs     lr, spsr
 503         /* save spsr in position 1 of saved stack */
 504         str     lr, [r13, #4]
 505
 506         /* prepare SVC-Mode */
 507         mov     r13, #MODE_SVC
 508         @ msr   spsr_c, r13
 509         /* switch modes, make sure moves will execute */
 510         msr     spsr, r13
 511         /* capture return pc */
 512         mov     lr, pc
 513         /* jump to next instruction & switch modes. */
 514         movs    pc, lr
 515         .endm
 516
 517         .macro get_bad_stack_swi
 518         /* space on current stack for scratch reg. */
 519         sub     r13, r13, #4
 520         /* save R0's value. */
 521         str     r0, [r13]
 522         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 523         /* save caller lr in position 0 of saved stack */
 524         str     lr, [r0]
 525         /* get the spsr */
 526         mrs     r0, spsr
 527         /* save spsr in position 1 of saved stack */
 528         str     lr, [r0, #4]
 529         /* restore r0 */
 530         ldr     r0, [r13]
 531         /* pop stack entry */
 532         add     r13, r13, #4
 533         .endm
 534
 535 /*
 536  * exception handlers
 537  */
 538         .align  5
 539 undefined_instruction:
 540         get_bad_stack
 541         bad_save_user_regs
 542         bl      do_undefined_instruction
 543
 544         .align  5
 545 software_interrupt:
 546         get_bad_stack_swi
 547         bad_save_user_regs
 548         bl      do_software_interrupt
 549
 550         .align  5
 551 prefetch_abort:
 552         get_bad_stack
 553         bad_save_user_regs
 554         bl      do_prefetch_abort
 555
 556         .align  5
 557 data_abort:
 558         get_bad_stack
 559         bad_save_user_regs
 560         bl      do_data_abort
 561
 562         .align  5
 563 not_used:
 564         get_bad_stack
 565         bad_save_user_regs
 566         bl      do_not_used
 567
 568         .align  5
 569 irq:
 570         get_bad_stack
 571         bad_save_user_regs
 572         bl      do_irq
 573
 574         .align  5
 575 fiq:
 576         get_bad_stack
 577         bad_save_user_regs
 578         bl      do_fiq
 579 #endif /* CONFIG_NAND_SPL */