arch/arm/cpu/arm720t/start.S

   1 /*
   2  *  armboot - Startup Code for ARM720 CPU-core
   3  *
   4  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   5  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <asm-offsets.h>
  27 #include <config.h>
  28 #include <version.h>
  29 #include <asm/hardware.h>
  30
  31 /*
  32  *************************************************************************
  33  *
  34  * Jump vector table as in table 3.1 in [1]
  35  *
  36  *************************************************************************
  37  */
  38
  39
  40 .globl _start
  41 _start: b       reset
  42         ldr     pc, _undefined_instruction
  43         ldr     pc, _software_interrupt
  44         ldr     pc, _prefetch_abort
  45         ldr     pc, _data_abort
  46         ldr     pc, _not_used
  47         ldr     pc, _irq
  48         ldr     pc, _fiq
  49
  50 #ifdef CONFIG_SPL_BUILD
  51 _undefined_instruction: .word _undefined_instruction
  52 _software_interrupt:    .word _software_interrupt
  53 _prefetch_abort:        .word _prefetch_abort
  54 _data_abort:            .word _data_abort
  55 _not_used:              .word _not_used
  56 _irq:                   .word _irq
  57 _fiq:                   .word _fiq
  58 _pad:                   .word 0x12345678 /* now 16*4=64 */
  59 #else
  60 _undefined_instruction: .word undefined_instruction
  61 _software_interrupt:    .word software_interrupt
  62 _prefetch_abort:        .word prefetch_abort
  63 _data_abort:            .word data_abort
  64 _not_used:              .word not_used
  65 _irq:                   .word irq
  66 _fiq:                   .word fiq
  67 _pad:                   .word 0x12345678 /* now 16*4=64 */
  68 #endif  /* CONFIG_SPL_BUILD */
  69
  70         .balignl 16,0xdeadbeef
  71
  72
  73 /*
  74  *************************************************************************
  75  *
  76  * Startup Code (reset vector)
  77  *
  78  * do important init only if we don't start from RAM!
  79  * relocate armboot to ram
  80  * setup stack
  81  * jump to second stage
  82  *
  83  *************************************************************************
  84  */
  85
  86 .globl _TEXT_BASE
  87 _TEXT_BASE:
  88 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
  89         .word   CONFIG_SPL_TEXT_BASE
  90 #else
  91         .word   CONFIG_SYS_TEXT_BASE
  92 #endif
  93
  94 /*
  95  * These are defined in the board-specific linker script.
  96  * Subtracting _start from them lets the linker put their
  97  * relative position in the executable instead of leaving
  98  * them null.
  99  */
 100 .globl _bss_start_ofs
 101 _bss_start_ofs:
 102         .word __bss_start - _start
 103
 104 .globl _image_copy_end_ofs
 105 _image_copy_end_ofs:
 106         .word __image_copy_end - _start
 107
 108 .globl _bss_end_ofs
 109 _bss_end_ofs:
 110         .word __bss_end - _start
 111
 112 .globl _end_ofs
 113 _end_ofs:
 114         .word _end - _start
 115
 116 #ifdef CONFIG_USE_IRQ
 117 /* IRQ stack memory (calculated at run-time) */
 118 .globl IRQ_STACK_START
 119 IRQ_STACK_START:
 120         .word   0x0badc0de
 121
 122 /* IRQ stack memory (calculated at run-time) */
 123 .globl FIQ_STACK_START
 124 FIQ_STACK_START:
 125         .word 0x0badc0de
 126 #endif
 127
 128 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 129 .globl IRQ_STACK_START_IN
 130 IRQ_STACK_START_IN:
 131         .word   0x0badc0de
 132
 133 /*
 134  * the actual reset code
 135  */
 136
 137 reset:
 138         /*
 139          * set the cpu to SVC32 mode
 140          */
 141         mrs     r0,cpsr
 142         bic     r0,r0,#0x1f
 143         orr     r0,r0,#0xd3
 144         msr     cpsr,r0
 145
 146         /*
 147          * we do sys-critical inits only at reboot,
 148          * not when booting from ram!
 149          */
 150 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 151         bl      cpu_init_crit
 152 #endif
 153
 154         bl      _main
 155
 156 /*------------------------------------------------------------------------------*/
 157
 158 /*
 159  * void relocate_code(addr_moni)
 160  *
 161  * This function relocates the monitor code.
 162  */
 163         .globl  relocate_code
 164 relocate_code:
 165         mov     r6, r0  /* save addr of destination */
 166
 167         adr     r0, _start
 168         subs    r9, r6, r0              /* r9 <- relocation offset */
 169         beq     relocate_done           /* skip relocation */
 170         mov     r1, r6                  /* r1 <- scratch for copy_loop */
 171         ldr     r3, _image_copy_end_ofs
 172         add     r2, r0, r3              /* r2 <- source end address         */
 173
 174 copy_loop:
 175         ldmia   r0!, {r10-r11}          /* copy from source address [r0]    */
 176         stmia   r1!, {r10-r11}          /* copy to   target address [r1]    */
 177         cmp     r0, r2                  /* until source end address [r2]    */
 178         blo     copy_loop
 179
 180 #ifndef CONFIG_SPL_BUILD
 181         /*
 182          * fix .rel.dyn relocations
 183          */
 184         ldr     r0, _TEXT_BASE          /* r0 <- Text base */
 185         ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
 186         add     r10, r10, r0            /* r10 <- sym table in FLASH */
 187         ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
 188         add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
 189         ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
 190         add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
 191 fixloop:
 192         ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
 193         add     r0, r0, r9              /* r0 <- location to fix up in RAM */
 194         ldr     r1, [r2, #4]
 195         and     r7, r1, #0xff
 196         cmp     r7, #23                 /* relative fixup? */
 197         beq     fixrel
 198         cmp     r7, #2                  /* absolute fixup? */
 199         beq     fixabs
 200         /* ignore unknown type of fixup */
 201         b       fixnext
 202 fixabs:
 203         /* absolute fix: set location to (offset) symbol value */
 204         mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
 205         add     r1, r10, r1             /* r1 <- address of symbol in table */
 206         ldr     r1, [r1, #4]            /* r1 <- symbol value */
 207         add     r1, r1, r9              /* r1 <- relocated sym addr */
 208         b       fixnext
 209 fixrel:
 210         /* relative fix: increase location by offset */
 211         ldr     r1, [r0]
 212         add     r1, r1, r9
 213 fixnext:
 214         str     r1, [r0]
 215         add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
 216         cmp     r2, r3
 217         blo     fixloop
 218 #endif
 219
 220 relocate_done:
 221
 222         mov     pc, lr
 223
 224 _rel_dyn_start_ofs:
 225         .word __rel_dyn_start - _start
 226 _rel_dyn_end_ofs:
 227         .word __rel_dyn_end - _start
 228 _dynsym_start_ofs:
 229         .word __dynsym_start - _start
 230
 231         .globl  c_runtime_cpu_setup
 232 c_runtime_cpu_setup:
 233
 234         mov     pc, lr
 235
 236 /*
 237  *************************************************************************
 238  *
 239  * CPU_init_critical registers
 240  *
 241  * setup important registers
 242  * setup memory timing
 243  *
 244  *************************************************************************
 245  */
 246
 247 cpu_init_crit:
 248
 249 #if !defined(CONFIG_TEGRA)
 250         mov     ip, lr
 251         /*
 252          * before relocating, we have to setup RAM timing
 253          * because memory timing is board-dependent, you will
 254          * find a lowlevel_init.S in your board directory.
 255          */
 256         bl      lowlevel_init
 257         mov     lr, ip
 258 #endif
 259
 260         mov     pc, lr
 261
 262
 263 #ifndef CONFIG_SPL_BUILD
 264 /*
 265  *************************************************************************
 266  *
 267  * Interrupt handling
 268  *
 269  *************************************************************************
 270  */
 271
 272 @
 273 @ IRQ stack frame.
 274 @
 275 #define S_FRAME_SIZE    72
 276
 277 #define S_OLD_R0        68
 278 #define S_PSR           64
 279 #define S_PC            60
 280 #define S_LR            56
 281 #define S_SP            52
 282
 283 #define S_IP            48
 284 #define S_FP            44
 285 #define S_R10           40
 286 #define S_R9            36
 287 #define S_R8            32
 288 #define S_R7            28
 289 #define S_R6            24
 290 #define S_R5            20
 291 #define S_R4            16
 292 #define S_R3            12
 293 #define S_R2            8
 294 #define S_R1            4
 295 #define S_R0            0
 296
 297 #define MODE_SVC 0x13
 298 #define I_BIT    0x80
 299
 300 /*
 301  * use bad_save_user_regs for abort/prefetch/undef/swi ...
 302  * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 303  */
 304
 305         .macro  bad_save_user_regs
 306         sub     sp, sp, #S_FRAME_SIZE
 307         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 308         add     r8, sp, #S_PC
 309
 310         ldr     r2, IRQ_STACK_START_IN
 311         ldmia   r2, {r2 - r4}                   @ get pc, cpsr, old_r0
 312         add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
 313
 314         add     r5, sp, #S_SP
 315         mov     r1, lr
 316         stmia   r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
 317         mov     r0, sp
 318         .endm
 319
 320         .macro  irq_save_user_regs
 321         sub     sp, sp, #S_FRAME_SIZE
 322         stmia   sp, {r0 - r12}                  @ Calling r0-r12
 323         add     r8, sp, #S_PC
 324         stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 325         str     lr, [r8, #0]                    @ Save calling PC
 326         mrs     r6, spsr
 327         str     r6, [r8, #4]                    @ Save CPSR
 328         str     r0, [r8, #8]                    @ Save OLD_R0
 329         mov     r0, sp
 330         .endm
 331
 332         .macro  irq_restore_user_regs
 333         ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 334         mov     r0, r0
 335         ldr     lr, [sp, #S_PC]                 @ Get PC
 336         add     sp, sp, #S_FRAME_SIZE
 337         subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 338         .endm
 339
 340         .macro get_bad_stack
 341         ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
 342
 343         str     lr, [r13]                       @ save caller lr / spsr
 344         mrs     lr, spsr
 345         str     lr, [r13, #4]
 346
 347         mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 348         msr     spsr_c, r13
 349         mov     lr, pc
 350         movs    pc, lr
 351         .endm
 352
 353         .macro get_irq_stack                    @ setup IRQ stack
 354         ldr     sp, IRQ_STACK_START
 355         .endm
 356
 357         .macro get_fiq_stack                    @ setup FIQ stack
 358         ldr     sp, FIQ_STACK_START
 359         .endm
 360
 361 /*
 362  * exception handlers
 363  */
 364         .align  5
 365 undefined_instruction:
 366         get_bad_stack
 367         bad_save_user_regs
 368         bl      do_undefined_instruction
 369
 370         .align  5
 371 software_interrupt:
 372         get_bad_stack
 373         bad_save_user_regs
 374         bl      do_software_interrupt
 375
 376         .align  5
 377 prefetch_abort:
 378         get_bad_stack
 379         bad_save_user_regs
 380         bl      do_prefetch_abort
 381
 382         .align  5
 383 data_abort:
 384         get_bad_stack
 385         bad_save_user_regs
 386         bl      do_data_abort
 387
 388         .align  5
 389 not_used:
 390         get_bad_stack
 391         bad_save_user_regs
 392         bl      do_not_used
 393
 394 #ifdef CONFIG_USE_IRQ
 395
 396         .align  5
 397 irq:
 398         get_irq_stack
 399         irq_save_user_regs
 400         bl      do_irq
 401         irq_restore_user_regs
 402
 403         .align  5
 404 fiq:
 405         get_fiq_stack
 406         /* someone ought to write a more effiction fiq_save_user_regs */
 407         irq_save_user_regs
 408         bl      do_fiq
 409         irq_restore_user_regs
 410
 411 #else
 412
 413         .align  5
 414 irq:
 415         get_bad_stack
 416         bad_save_user_regs
 417         bl      do_irq
 418
 419         .align  5
 420 fiq:
 421         get_bad_stack
 422         bad_save_user_regs
 423         bl      do_fiq
 424
 425 #endif
 426 #endif /* CONFIG_SPL_BUILD */