arch/arm/cpu/arm720t/tegra-common/cpu.c

   1 /*
   2  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <common.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gp_padctrl.h>
  21 #include <asm/arch/pinmux.h>
  22 #include <asm/arch/tegra.h>
  23 #include <asm/arch-tegra/clk_rst.h>
  24 #include <asm/arch-tegra/pmc.h>
  25 #include <asm/arch-tegra/scu.h>
  26 #include "cpu.h"
  27
  28 int get_num_cpus(void)
  29 {
  30         struct apb_misc_gp_ctlr *gp;
  31         uint rev;
  32
  33         gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  34         rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  35
  36         switch (rev) {
  37         case CHIPID_TEGRA20:
  38                 return 2;
  39                 break;
  40         case CHIPID_TEGRA30:
  41         case CHIPID_TEGRA114:
  42         default:
  43                 return 4;
  44                 break;
  45         }
  46 }
  47
  48 /*
  49  * Timing tables for each SOC for all four oscillator options.
  50  */
  51 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  52         /*
  53          * T20: 1 GHz
  54          *
  55          * Register   Field  Bits   Width
  56          * ------------------------------
  57          * PLLX_BASE  p      22:20    3
  58          * PLLX_BASE  n      17: 8   10
  59          * PLLX_BASE  m       4: 0    5
  60          * PLLX_MISC  cpcon  11: 8    4
  61          */
  62         {
  63                 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  64                 { .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
  65                 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  66                 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  67         },
  68         /*
  69          * T25: 1.2 GHz
  70          *
  71          * Register   Field  Bits   Width
  72          * ------------------------------
  73          * PLLX_BASE  p      22:20    3
  74          * PLLX_BASE  n      17: 8   10
  75          * PLLX_BASE  m       4: 0    5
  76          * PLLX_MISC  cpcon  11: 8    4
  77          */
  78         {
  79                 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  80                 { .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
  81                 { .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  82                 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  83         },
  84         /*
  85          * T30: 1.4 GHz
  86          *
  87          * Register   Field  Bits   Width
  88          * ------------------------------
  89          * PLLX_BASE  p      22:20    3
  90          * PLLX_BASE  n      17: 8   10
  91          * PLLX_BASE  m       4: 0    5
  92          * PLLX_MISC  cpcon  11: 8    4
  93          */
  94         {
  95                 { .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
  96                 { .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
  97                 { .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
  98                 { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
  99         },
 100         /*
 101          * T114: 700 MHz
 102          *
 103          * Register   Field  Bits   Width
 104          * ------------------------------
 105          * PLLX_BASE  p      23:20    4
 106          * PLLX_BASE  n      15: 8    8
 107          * PLLX_BASE  m       7: 0    8
 108          */
 109         {
 110                 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
 111                 { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
 112                 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
 113                 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 114         },
 115 };
 116
 117 void adjust_pllp_out_freqs(void)
 118 {
 119         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 120         struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
 121         u32 reg;
 122
 123         /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
 124         reg = readl(&pll->pll_out[0]);  /* OUTA, contains OUT2 / OUT1 */
 125         reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
 126                 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
 127         writel(reg, &pll->pll_out[0]);
 128
 129         reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
 130         reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
 131                 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
 132         writel(reg, &pll->pll_out[1]);
 133 }
 134
 135 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 136                 u32 divp, u32 cpcon)
 137 {
 138         int chip = tegra_get_chip();
 139         u32 reg;
 140
 141         /* If PLLX is already enabled, just return */
 142         if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
 143                 debug("pllx_set_rate: PLLX already enabled, returning\n");
 144                 return 0;
 145         }
 146
 147         debug(" pllx_set_rate entry\n");
 148
 149         /* Set BYPASS, m, n and p to PLLX_BASE */
 150         reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
 151         reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
 152         writel(reg, &pll->pll_base);
 153
 154         /* Set cpcon to PLLX_MISC */
 155         if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
 156                 reg = (cpcon << PLL_CPCON_SHIFT);
 157         else
 158                 reg = 0;
 159
 160         /* Set dccon to PLLX_MISC if freq > 600MHz */
 161         if (divn > 600)
 162                 reg |= (1 << PLL_DCCON_SHIFT);
 163         writel(reg, &pll->pll_misc);
 164
 165         /* Enable PLLX */
 166         reg = readl(&pll->pll_base);
 167         reg |= PLL_ENABLE_MASK;
 168
 169         /* Disable BYPASS */
 170         reg &= ~PLL_BYPASS_MASK;
 171         writel(reg, &pll->pll_base);
 172
 173         /* Set lock_enable to PLLX_MISC */
 174         reg = readl(&pll->pll_misc);
 175         reg |= PLL_LOCK_ENABLE_MASK;
 176         writel(reg, &pll->pll_misc);
 177
 178         return 0;
 179 }
 180
 181 void init_pllx(void)
 182 {
 183         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 184         struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
 185         int soc_type, sku_info, chip_sku;
 186         enum clock_osc_freq osc;
 187         struct clk_pll_table *sel;
 188
 189         debug("init_pllx entry\n");
 190
 191         /* get SOC (chip) type */
 192         soc_type = tegra_get_chip();
 193         debug(" init_pllx: SoC = 0x%02X\n", soc_type);
 194
 195         /* get SKU info */
 196         sku_info = tegra_get_sku_info();
 197         debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
 198
 199         /* get chip SKU, combo of the above info */
 200         chip_sku = tegra_get_chip_sku();
 201         debug(" init_pllx: Chip SKU = %d\n", chip_sku);
 202
 203         /* get osc freq */
 204         osc = clock_get_osc_freq();
 205         debug(" init_pllx: osc = %d\n", osc);
 206
 207         /* set pllx */
 208         sel = &tegra_pll_x_table[chip_sku][osc];
 209         pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
 210
 211         /* adjust PLLP_out1-4 on T3x/T114 */
 212         if (soc_type >= CHIPID_TEGRA30) {
 213                 debug("  init_pllx: adjusting PLLP out freqs\n");
 214                 adjust_pllp_out_freqs();
 215         }
 216 }
 217
 218 void enable_cpu_clock(int enable)
 219 {
 220         struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 221         u32 clk;
 222
 223         /*
 224          * NOTE:
 225          * Regardless of whether the request is to enable or disable the CPU
 226          * clock, every processor in the CPU complex except the master (CPU 0)
 227          * will have it's clock stopped because the AVP only talks to the
 228          * master.
 229          */
 230
 231         if (enable) {
 232                 /* Initialize PLLX */
 233                 init_pllx();
 234
 235                 /* Wait until all clocks are stable */
 236                 udelay(PLL_STABILIZATION_DELAY);
 237
 238                 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
 239                 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
 240         }
 241
 242         /*
 243          * Read the register containing the individual CPU clock enables and
 244          * always stop the clocks to CPUs > 0.
 245          */
 246         clk = readl(&clkrst->crc_clk_cpu_cmplx);
 247         clk |= 1 << CPU1_CLK_STP_SHIFT;
 248         if (get_num_cpus() == 4)
 249                 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
 250
 251         /* Stop/Unstop the CPU clock */
 252         clk &= ~CPU0_CLK_STP_MASK;
 253         clk |= !enable << CPU0_CLK_STP_SHIFT;
 254         writel(clk, &clkrst->crc_clk_cpu_cmplx);
 255
 256         clock_enable(PERIPH_ID_CPU);
 257 }
 258
 259 static int is_cpu_powered(void)
 260 {
 261         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 262
 263         return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 264 }
 265
 266 static void remove_cpu_io_clamps(void)
 267 {
 268         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 269         u32 reg;
 270
 271         /* Remove the clamps on the CPU I/O signals */
 272         reg = readl(&pmc->pmc_remove_clamping);
 273         reg |= CPU_CLMP;
 274         writel(reg, &pmc->pmc_remove_clamping);
 275
 276         /* Give I/O signals time to stabilize */
 277         udelay(IO_STABILIZATION_DELAY);
 278 }
 279
 280 void powerup_cpu(void)
 281 {
 282         struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 283         u32 reg;
 284         int timeout = IO_STABILIZATION_DELAY;
 285
 286         if (!is_cpu_powered()) {
 287                 /* Toggle the CPU power state (OFF -> ON) */
 288                 reg = readl(&pmc->pmc_pwrgate_toggle);
 289                 reg &= PARTID_CP;
 290                 reg |= START_CP;
 291                 writel(reg, &pmc->pmc_pwrgate_toggle);
 292
 293                 /* Wait for the power to come up */
 294                 while (!is_cpu_powered()) {
 295                         if (timeout-- == 0)
 296                                 printf("CPU failed to power up!\n");
 297                         else
 298                                 udelay(10);
 299                 }
 300
 301                 /*
 302                  * Remove the I/O clamps from CPU power partition.
 303                  * Recommended only on a Warm boot, if the CPU partition gets
 304                  * power gated. Shouldn't cause any harm when called after a
 305                  * cold boot according to HW, probably just redundant.
 306                  */
 307                 remove_cpu_io_clamps();
 308         }
 309 }
 310
 311 void reset_A9_cpu(int reset)
 312 {
 313         /*
 314         * NOTE:  Regardless of whether the request is to hold the CPU in reset
 315         *        or take it out of reset, every processor in the CPU complex
 316         *        except the master (CPU 0) will be held in reset because the
 317         *        AVP only talks to the master. The AVP does not know that there
 318         *        are multiple processors in the CPU complex.
 319         */
 320         int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
 321         int num_cpus = get_num_cpus();
 322         int cpu;
 323
 324         debug("reset_a9_cpu entry\n");
 325         /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
 326         for (cpu = 1; cpu < num_cpus; cpu++)
 327                 reset_cmplx_set_enable(cpu, mask, 1);
 328         reset_cmplx_set_enable(0, mask, reset);
 329
 330         /* Enable/Disable master CPU reset */
 331         reset_set_enable(PERIPH_ID_CPU, reset);
 332 }
 333
 334 void clock_enable_coresight(int enable)
 335 {
 336         u32 rst, src = 2;
 337         int soc_type;
 338
 339         debug("clock_enable_coresight entry\n");
 340         clock_set_enable(PERIPH_ID_CORESIGHT, enable);
 341         reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
 342
 343         if (enable) {
 344                 /*
 345                  * Put CoreSight on PLLP_OUT0 and divide it down as per
 346                  * PLLP base frequency based on SoC type (T20/T30/T114).
 347                  * Clock divider request would setup CSITE clock as 144MHz
 348                  * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 349                  */
 350
 351                 soc_type = tegra_get_chip();
 352                 if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
 353                         src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
 354                 else if (soc_type == CHIPID_TEGRA20)
 355                         src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
 356                 else
 357                         printf("%s: Unknown SoC type %X!\n",
 358                                  __func__, soc_type);
 359
 360                 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 361
 362                 /* Unlock the CPU CoreSight interfaces */
 363                 rst = CORESIGHT_UNLOCK;
 364                 writel(rst, CSITE_CPU_DBG0_LAR);
 365                 writel(rst, CSITE_CPU_DBG1_LAR);
 366                 if (get_num_cpus() == 4) {
 367                         writel(rst, CSITE_CPU_DBG2_LAR);
 368                         writel(rst, CSITE_CPU_DBG3_LAR);
 369                 }
 370         }
 371 }
 372
 373 void halt_avp(void)
 374 {
 375         for (;;) {
 376                 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
 377                         | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
 378                         FLOW_CTLR_HALT_COP_EVENTS);
 379         }
 380 }