arch/arm/cpu/arm920t/s3c24x0/speed.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002
   6  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /* This code should work for both the S3C2400 and the S3C2410
  12  * as they seem to have the same PLL and clock machinery inside.
  13  * The different address mapping is handled by the s3c24xx.h files below.
  14  */
  15
  16 #include <common.h>
  17 #ifdef CONFIG_S3C24X0
  18
  19 #include <asm/io.h>
  20 #include <asm/arch/s3c24x0_cpu.h>
  21
  22 #define MPLL 0
  23 #define UPLL 1
  24
  25 /* ------------------------------------------------------------------------- */
  26 /* NOTE: This describes the proper use of this file.
  27  *
  28  * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  29  *
  30  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  31  * the specified bus in HZ.
  32  */
  33 /* ------------------------------------------------------------------------- */
  34
  35 static ulong get_PLLCLK(int pllreg)
  36 {
  37         struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  38         ulong r, m, p, s;
  39
  40         if (pllreg == MPLL)
  41                 r = readl(&clk_power->mpllcon);
  42         else if (pllreg == UPLL)
  43                 r = readl(&clk_power->upllcon);
  44         else
  45                 hang();
  46
  47         m = ((r & 0xFF000) >> 12) + 8;
  48         p = ((r & 0x003F0) >> 4) + 2;
  49         s = r & 0x3;
  50
  51 #if defined(CONFIG_S3C2440)
  52         if (pllreg == MPLL)
  53                 return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
  54 #endif
  55         return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
  56
  57 }
  58
  59 /* return FCLK frequency */
  60 ulong get_FCLK(void)
  61 {
  62         return get_PLLCLK(MPLL);
  63 }
  64
  65 /* return HCLK frequency */
  66 ulong get_HCLK(void)
  67 {
  68         struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  69 #ifdef CONFIG_S3C2440
  70         switch (readl(&clk_power->clkdivn) & 0x6) {
  71         default:
  72         case 0:
  73                 return get_FCLK();
  74         case 2:
  75                 return get_FCLK() / 2;
  76         case 4:
  77                 return (readl(&clk_power->camdivn) & (1 << 9)) ?
  78                         get_FCLK() / 8 : get_FCLK() / 4;
  79         case 6:
  80                 return (readl(&clk_power->camdivn) & (1 << 8)) ?
  81                         get_FCLK() / 6 : get_FCLK() / 3;
  82         }
  83 #else
  84         return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
  85 #endif
  86 }
  87
  88 /* return PCLK frequency */
  89 ulong get_PCLK(void)
  90 {
  91         struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
  92
  93         return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
  94 }
  95
  96 /* return UCLK frequency */
  97 ulong get_UCLK(void)
  98 {
  99         return get_PLLCLK(UPLL);
 100 }
 101
 102 #endif /* CONFIG_S3C24X0 */