arch/arm/cpu/arm926ejs/armada100/cpu.c

   1 /*
   2  * (C) Copyright 2010
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  * Contributor: Mahavir Jain <mjain@marvell.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/armada100.h>
  13
  14 #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
  15 #define SET_MRVL_ID     (1<<8)
  16 #define L2C_RAM_SEL     (1<<4)
  17
  18 int arch_cpu_init(void)
  19 {
  20         u32 val;
  21         struct armd1cpu_registers *cpuregs =
  22                 (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  23
  24         struct armd1apb1_registers *apb1clkres =
  25                 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  26
  27         struct armd1mpmu_registers *mpmu =
  28                 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  29
  30         /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
  31         val = readl(&cpuregs->cpu_conf);
  32         val = val | SET_MRVL_ID;
  33         writel(val, &cpuregs->cpu_conf);
  34
  35         /* Enable Clocks for all hardware units */
  36         writel(0xFFFFFFFF, &mpmu->acgr);
  37
  38         /* Turn on AIB and AIB-APB Functional clock */
  39         writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
  40
  41         /* ensure L2 cache is not mapped as SRAM */
  42         val = readl(&cpuregs->cpu_conf);
  43         val = val & ~(L2C_RAM_SEL);
  44         writel(val, &cpuregs->cpu_conf);
  45
  46         /* Enable GPIO clock */
  47         writel(APBC_APBCLK, &apb1clkres->gpio);
  48
  49 #ifdef CONFIG_I2C_MV
  50         /* Enable general I2C clock */
  51         writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  52         writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
  53
  54         /* Enable power I2C clock */
  55         writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  56         writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
  57 #endif
  58
  59         /*
  60          * Enable Functional and APB clock at 14.7456MHz
  61          * for configured UART console
  62          */
  63 #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
  64         writel(UARTCLK14745KHZ, &apb1clkres->uart3);
  65 #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
  66         writel(UARTCLK14745KHZ, &apb1clkres->uart2);
  67 #else
  68         writel(UARTCLK14745KHZ, &apb1clkres->uart1);
  69 #endif
  70         icache_enable();
  71
  72         return 0;
  73 }
  74
  75 #if defined(CONFIG_DISPLAY_CPUINFO)
  76 int print_cpuinfo(void)
  77 {
  78         u32 id;
  79         struct armd1cpu_registers *cpuregs =
  80                 (struct armd1cpu_registers *) ARMD1_CPU_BASE;
  81
  82         id = readl(&cpuregs->chip_id);
  83         printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
  84         return 0;
  85 }
  86 #endif
  87
  88 #ifdef CONFIG_I2C_MV
  89 void i2c_clk_enable(void)
  90 {
  91 }
  92 #endif