arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c

   1 /*
   2  * SoC-specific lowlevel code for DA850
   3  *
   4  * Copyright (C) 2011
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <nand.h>
  11 #include <ns16550.h>
  12 #include <post.h>
  13 #include <asm/arch/da850_lowlevel.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/davinci_misc.h>
  16 #include <asm/arch/ddr2_defs.h>
  17 #include <asm/ti-common/davinci_nand.h>
  18 #include <asm/arch/pll_defs.h>
  19
  20 void davinci_enable_uart0(void)
  21 {
  22         lpsc_on(DAVINCI_LPSC_UART0);
  23
  24         /* Bringup UART0 out of reset */
  25         REG(UART0_PWREMU_MGMT) = 0x00006001;
  26 }
  27
  28 #if defined(CONFIG_SYS_DA850_PLL_INIT)
  29 static void da850_waitloop(unsigned long loopcnt)
  30 {
  31         unsigned long   i;
  32
  33         for (i = 0; i < loopcnt; i++)
  34                 asm("   NOP");
  35 }
  36
  37 static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
  38 {
  39         if (reg == davinci_pllc0_regs)
  40                 /* Unlock PLL registers. */
  41                 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
  42
  43         /*
  44          * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
  45          * through MMR
  46          */
  47         clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
  48         /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  49         clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
  50
  51         /* Set PLLEN=0 => PLL BYPASS MODE */
  52         clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  53
  54         da850_waitloop(150);
  55
  56         if (reg == davinci_pllc0_regs) {
  57                 /*
  58                  * Select the Clock Mode bit 8 as External Clock or On Chip
  59                  * Oscilator
  60                  */
  61                 dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
  62                 setbits_le32(&reg->pllctl,
  63                         (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
  64         }
  65
  66         /* Clear PLLRST bit to reset the PLL */
  67         clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  68
  69         /* Disable the PLL output */
  70         setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  71
  72         /* PLL initialization sequence */
  73         /*
  74          * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
  75          * power down bit
  76          */
  77         clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
  78
  79         /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
  80         clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  81
  82 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
  83         /* program the prediv */
  84         if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
  85                 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
  86                         &reg->prediv);
  87 #endif
  88
  89         /* Program the required multiplier value in PLLM */
  90         writel(pllmult, &reg->pllm);
  91
  92         /* program the postdiv */
  93         if (reg == davinci_pllc0_regs)
  94                 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
  95                         &reg->postdiv);
  96         else
  97                 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
  98                         &reg->postdiv);
  99
 100         /*
 101          * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
 102          * no GO operation is currently in progress
 103          */
 104         while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
 105                 ;
 106
 107         if (reg == davinci_pllc0_regs) {
 108                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
 109                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
 110                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
 111                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
 112                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
 113                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
 114                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
 115         } else {
 116                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
 117                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
 118                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
 119         }
 120
 121         /*
 122          * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
 123          * transition.
 124          */
 125         setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
 126
 127         /*
 128          * Wait for the GOSTAT bit in PLLSTAT to clear to 0
 129          * (completion of phase alignment).
 130          */
 131         while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
 132                 ;
 133
 134         /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
 135         da850_waitloop(200);
 136
 137         /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
 138         setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
 139
 140         /* Wait for PLL to lock. See PLL spec for PLL lock time */
 141         da850_waitloop(2400);
 142
 143         /*
 144          * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
 145          * mode
 146          */
 147         setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
 148
 149
 150         /*
 151          * clear EMIFA and EMIFB clock source settings, let them
 152          * run off SYSCLK
 153          */
 154         if (reg == davinci_pllc0_regs)
 155                 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
 156                         ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
 157
 158         return 0;
 159 }
 160 #endif /* CONFIG_SYS_DA850_PLL_INIT */
 161
 162 #if defined(CONFIG_SYS_DA850_DDR_INIT)
 163 static int da850_ddr_setup(void)
 164 {
 165         unsigned long   tmp;
 166
 167         /* Enable the Clock to DDR2/mDDR */
 168         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 169
 170         tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 171         if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
 172                 /* Begin VTP Calibration */
 173                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 174                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
 175                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 176                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 177                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 178
 179                 /* Polling READY bit to see when VTP calibration is done */
 180                 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 181                 while ((tmp & VTP_READY) != VTP_READY)
 182                         tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 183
 184                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
 185                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 186         }
 187         setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
 188         writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 189
 190         if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
 191                 /* DDR2 */
 192                 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 193                         (1 << DDR_SLEW_DDR_PDENA_BIT) |
 194                         (1 << DDR_SLEW_CMOSEN_BIT));
 195         } else {
 196                 /* MOBILE DDR */
 197                 setbits_le32(&davinci_syscfg1_regs->ddr_slew,
 198                         (1 << DDR_SLEW_DDR_PDENA_BIT) |
 199                         (1 << DDR_SLEW_CMOSEN_BIT));
 200         }
 201
 202         /*
 203          * SDRAM Configuration Register (SDCR):
 204          * First set the BOOTUNLOCK bit to make configuration bits
 205          * writeable.
 206          */
 207         setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
 208
 209         /*
 210          * Write the new value of these bits and clear BOOTUNLOCK.
 211          * At the same time, set the TIMUNLOCK bit to allow changing
 212          * the timing registers
 213          */
 214         tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
 215         tmp &= ~DV_DDR_BOOTUNLOCK;
 216         tmp |= DV_DDR_TIMUNLOCK;
 217         writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 218
 219         /* write memory configuration and timing */
 220         if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
 221                 /* MOBILE DDR only*/
 222                 writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
 223                         &dv_ddr2_regs_ctrl->sdbcr2);
 224         }
 225         writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
 226         writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 227
 228         /* clear the TIMUNLOCK bit and write the value of the CL field */
 229         tmp &= ~DV_DDR_TIMUNLOCK;
 230         writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 231
 232         /*
 233          * LPMODEN and MCLKSTOPEN must be set!
 234          * Without this bits set, PSC don;t switch states !!
 235          */
 236         writel(CONFIG_SYS_DA850_DDR2_SDRCR |
 237                 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
 238                 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
 239                 &dv_ddr2_regs_ctrl->sdrcr);
 240
 241         /* SyncReset the Clock to EMIF3A SDRAM */
 242         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 243         /* Enable the Clock to EMIF3A SDRAM */
 244         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 245
 246         /* disable self refresh */
 247         clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
 248                 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
 249         writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 250
 251         return 0;
 252 }
 253 #endif /* CONFIG_SYS_DA850_DDR_INIT */
 254
 255 __attribute__((weak))
 256 void board_gpio_init(void)
 257 {
 258         return;
 259 }
 260
 261 int arch_cpu_init(void)
 262 {
 263         /* Unlock kick registers */
 264         writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
 265         writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
 266
 267         dv_maskbits(&davinci_syscfg_regs->suspsrc,
 268                 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
 269
 270         /* configure pinmux settings */
 271         if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
 272                 return 1;
 273
 274 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 275         /* PLL setup */
 276         da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
 277         da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
 278 #endif
 279         /* setup CSn config */
 280 #if defined(CONFIG_SYS_DA850_CS2CFG)
 281         writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
 282 #endif
 283 #if defined(CONFIG_SYS_DA850_CS3CFG)
 284         writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 285 #endif
 286
 287         da8xx_configure_lpsc_items(lpsc, lpsc_size);
 288
 289         /* GPIO setup */
 290         board_gpio_init();
 291
 292
 293         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 294                         CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 295
 296         /*
 297          * Fix Power and Emulation Management Register
 298          * see sprufw3a.pdf page 37 Table 24
 299          */
 300         writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 301                 DAVINCI_UART_PWREMU_MGMT_UTRST),
 302 #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
 303                &davinci_uart0_ctrl_regs->pwremu_mgmt);
 304 #else
 305                &davinci_uart2_ctrl_regs->pwremu_mgmt);
 306 #endif
 307
 308 #if defined(CONFIG_SYS_DA850_DDR_INIT)
 309         da850_ddr_setup();
 310 #endif
 311
 312         return 0;
 313 }