3 * Texas Instruments <www.ti.com>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
13 * (C) Copyright 2002-2004
14 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
19 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
21 * SPDX-License-Identifier: GPL-2.0+
26 #include <asm/arch/timer_defs.h>
29 DECLARE_GLOBAL_DATA_PTR
;
31 static struct davinci_timer
* const timer
=
32 (struct davinci_timer
*)CONFIG_SYS_TIMERBASE
;
34 #define TIMER_LOAD_VAL 0xffffffff
36 #define TIM_CLK_DIV 16
40 /* We are using timer34 in unchained 32-bit mode, full speed */
41 writel(0x0, &timer
->tcr
);
42 writel(0x0, &timer
->tgcr
);
43 writel(0x06 | ((TIM_CLK_DIV
- 1) << 8), &timer
->tgcr
);
44 writel(0x0, &timer
->tim34
);
45 writel(TIMER_LOAD_VAL
, &timer
->prd34
);
46 writel(2 << 22, &timer
->tcr
);
47 gd
->arch
.timer_rate_hz
= CONFIG_SYS_HZ_CLOCK
/ TIM_CLK_DIV
;
48 gd
->arch
.timer_reset_value
= 0;
54 * Get the current 64 bit timer tick count
56 unsigned long long get_ticks(void)
58 unsigned long now
= readl(&timer
->tim34
);
60 /* increment tbu if tbl has rolled over */
61 if (now
< gd
->arch
.tbl
)
65 return (((unsigned long long)gd
->arch
.tbu
) << 32) | gd
->arch
.tbl
;
68 ulong
get_timer(ulong base
)
70 unsigned long long timer_diff
;
72 timer_diff
= get_ticks() - gd
->arch
.timer_reset_value
;
74 return lldiv(timer_diff
,
75 (gd
->arch
.timer_rate_hz
/ CONFIG_SYS_HZ
)) - base
;
78 void __udelay(unsigned long usec
)
80 unsigned long long endtime
;
82 endtime
= lldiv((unsigned long long)usec
* gd
->arch
.timer_rate_hz
,
84 endtime
+= get_ticks();
86 while (get_ticks() < endtime
)
91 * This function is derived from PowerPC code (timebase clock frequency).
92 * On ARM it returns the number of timer ticks per second.
96 return gd
->arch
.timer_rate_hz
;
99 #ifdef CONFIG_HW_WATCHDOG
100 static struct davinci_timer
* const wdttimer
=
101 (struct davinci_timer
*)CONFIG_SYS_WDTTIMERBASE
;
104 * See prufw2.pdf for using Timer as a WDT
106 void davinci_hw_watchdog_enable(void)
108 writel(0x0, &wdttimer
->tcr
);
109 writel(0x0, &wdttimer
->tgcr
);
111 writel(0x08 | 0x03 | ((TIM_CLK_DIV
- 1) << 8), &wdttimer
->tgcr
);
112 writel(CONFIG_SYS_WDT_PERIOD_LOW
, &wdttimer
->prd12
);
113 writel(CONFIG_SYS_WDT_PERIOD_HIGH
, &wdttimer
->prd34
);
114 writel(2 << 22, &wdttimer
->tcr
);
115 writel(0x0, &wdttimer
->tim12
);
116 writel(0x0, &wdttimer
->tim34
);
117 /* set WDEN bit, WDKEY 0xa5c6 */
118 writel(0xa5c64000, &wdttimer
->wdtcr
);
119 /* clear counter register */
120 writel(0xda7e4000, &wdttimer
->wdtcr
);
123 void davinci_hw_watchdog_reset(void)
125 writel(0xa5c64000, &wdttimer
->wdtcr
);
126 writel(0xda7e4000, &wdttimer
->wdtcr
);