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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/arm926ejs/kirkwood/cpu.c
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/cache.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <mvebu_mmc.h>
17 void reset_cpu(unsigned long ignored
)
19 struct kwcpu_registers
*cpureg
=
20 (struct kwcpu_registers
*)KW_CPU_REG_BASE
;
22 writel(readl(&cpureg
->rstoutn_mask
) | (1 << 2),
23 &cpureg
->rstoutn_mask
);
24 writel(readl(&cpureg
->sys_soft_rst
) | 1,
25 &cpureg
->sys_soft_rst
);
31 * Used with the Base register to set the address window size and location.
32 * Must be programmed from LSB to MSB as sequence of ones followed by
33 * sequence of zeros. The number of ones specifies the size of the window in
34 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
35 * NOTE: A value of 0x0 specifies 64-KByte size.
37 unsigned int kw_winctrl_calcsize(unsigned int sizeval
)
41 u32 val
= sizeval
>> 1;
43 for (i
= 0; val
>= 0x10000; i
++) {
47 return (0x0000ffff & j
);
51 * kw_config_adr_windows - Configure address Windows
53 * There are 8 address windows supported by Kirkwood Soc to addess different
54 * devices. Each window can be configured for size, BAR and remap addr
55 * Below configuration is standard for most of the cases
57 * If remap function not used, remap_lo must be set as base
59 * Reference Documentation:
60 * Mbus-L to Mbus Bridge Registers Configuration.
61 * (Sec 25.1 and 25.3 of Datasheet)
63 int kw_config_adr_windows(void)
65 struct kwwin_registers
*winregs
=
66 (struct kwwin_registers
*)KW_CPU_WIN_BASE
;
68 /* Window 0: PCIE MEM address space */
69 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE
,
70 KWCPU_ATTR_PCIE_MEM
, KWCPU_WIN_ENABLE
), &winregs
[0].ctrl
);
72 writel(KW_DEFADR_PCI_MEM
, &winregs
[0].base
);
73 writel(KW_DEFADR_PCI_MEM
, &winregs
[0].remap_lo
);
74 writel(0x0, &winregs
[0].remap_hi
);
76 /* Window 1: PCIE IO address space */
77 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE
,
78 KWCPU_ATTR_PCIE_IO
, KWCPU_WIN_ENABLE
), &winregs
[1].ctrl
);
79 writel(KW_DEFADR_PCI_IO
, &winregs
[1].base
);
80 writel(KW_DEFADR_PCI_IO_REMAP
, &winregs
[1].remap_lo
);
81 writel(0x0, &winregs
[1].remap_hi
);
83 /* Window 2: NAND Flash address space */
84 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY
,
85 KWCPU_ATTR_NANDFLASH
, KWCPU_WIN_ENABLE
), &winregs
[2].ctrl
);
86 writel(KW_DEFADR_NANDF
, &winregs
[2].base
);
87 writel(KW_DEFADR_NANDF
, &winregs
[2].remap_lo
);
88 writel(0x0, &winregs
[2].remap_hi
);
90 /* Window 3: SPI Flash address space */
91 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY
,
92 KWCPU_ATTR_SPIFLASH
, KWCPU_WIN_ENABLE
), &winregs
[3].ctrl
);
93 writel(KW_DEFADR_SPIF
, &winregs
[3].base
);
94 writel(KW_DEFADR_SPIF
, &winregs
[3].remap_lo
);
95 writel(0x0, &winregs
[3].remap_hi
);
97 /* Window 4: BOOT Memory address space */
98 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY
,
99 KWCPU_ATTR_BOOTROM
, KWCPU_WIN_ENABLE
), &winregs
[4].ctrl
);
100 writel(KW_DEFADR_BOOTROM
, &winregs
[4].base
);
102 /* Window 5: Security SRAM address space */
103 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM
,
104 KWCPU_ATTR_SASRAM
, KWCPU_WIN_ENABLE
), &winregs
[5].ctrl
);
105 writel(KW_DEFADR_SASRAM
, &winregs
[5].base
);
107 /* Window 6-7: Disabled */
108 writel(KWCPU_WIN_DISABLE
, &winregs
[6].ctrl
);
109 writel(KWCPU_WIN_DISABLE
, &winregs
[7].ctrl
);
115 * SYSRSTn Duration Counter Support
117 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
118 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
119 * The SYSRSTn duration counter is useful for implementing a manufacturer
120 * or factory reset. Upon a long reset assertion that is greater than a
121 * pre-configured environment variable value for sysrstdelay,
122 * The counter value is stored in the SYSRSTn Length Counter Register
123 * The counter is based on the 25-MHz reference clock (40ns)
124 * It is a 29-bit counter, yielding a maximum counting duration of
125 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
126 * it remains at this value until counter reset is triggered by setting
127 * bit 31 of KW_REG_SYSRST_CNT
129 static void kw_sysrst_action(void)
132 char *s
= getenv("sysrstcmd");
135 debug("Error.. %s failed, check sysrstcmd\n",
140 debug("Starting %s process...\n", __FUNCTION__
);
141 ret
= run_command(s
, 0);
143 debug("Error.. %s failed\n", __FUNCTION__
);
145 debug("%s process finished\n", __FUNCTION__
);
148 static void kw_sysrst_check(void)
150 u32 sysrst_cnt
, sysrst_dly
;
154 * no action if sysrstdelay environment variable is not defined
156 s
= getenv("sysrstdelay");
160 /* read sysrstdelay value */
161 sysrst_dly
= (u32
) simple_strtoul(s
, NULL
, 10);
163 /* read SysRst Length counter register (bits 28:0) */
164 sysrst_cnt
= (0x1fffffff & readl(KW_REG_SYSRST_CNT
));
165 debug("H/w Rst hold time: %d.%d secs\n",
166 sysrst_cnt
/ SYSRST_CNT_1SEC_VAL
,
167 sysrst_cnt
% SYSRST_CNT_1SEC_VAL
);
169 /* clear the counter for next valid read*/
170 writel(1 << 31, KW_REG_SYSRST_CNT
);
174 * if H/w Reset key is pressed and hold for time
175 * more than sysrst_dly in seconds
177 if (sysrst_cnt
>= SYSRST_CNT_1SEC_VAL
* sysrst_dly
)
181 #if defined(CONFIG_DISPLAY_CPUINFO)
182 int print_cpuinfo(void)
185 u16 devid
= (readl(KW_REG_PCIE_DEVID
) >> 16) & 0xffff;
186 u8 revid
= readl(KW_REG_PCIE_REVID
) & 0xff;
188 if ((readl(KW_REG_DEVICE_ID
) & 0x03) > 2) {
189 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__
, devid
);
197 else if (devid
== 0x6282)
213 printf("SoC: Kirkwood 88F%04x_%s\n", devid
, rev
);
216 #endif /* CONFIG_DISPLAY_CPUINFO */
218 #ifdef CONFIG_ARCH_CPU_INIT
219 int arch_cpu_init(void)
222 struct kwcpu_registers
*cpureg
=
223 (struct kwcpu_registers
*)KW_CPU_REG_BASE
;
225 /* Linux expects` the internal registers to be at 0xf1000000 */
226 writel(KW_REGS_PHY_BASE
, KW_OFFSET_REG
);
228 /* Enable and invalidate L2 cache in write through mode */
229 writel(readl(&cpureg
->l2_cfg
) | 0x18, &cpureg
->l2_cfg
);
230 invalidate_l2_cache();
232 kw_config_adr_windows();
234 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
236 * Configures the I/O voltage of the pads connected to Egigabit
237 * Ethernet interface to 1.8V
238 * By default it is set to 3.3V
240 reg
= readl(KW_REG_MPP_OUT_DRV_REG
);
242 writel(reg
, KW_REG_MPP_OUT_DRV_REG
);
244 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
246 * Set egiga port0/1 in normal functional mode
247 * This is required becasue on kirkwood by default ports are in reset mode
248 * OS egiga driver may not have provision to set them in normal mode
249 * and if u-boot is build without network support, network may fail at OS level
251 reg
= readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
252 reg
&= ~(1 << 4); /* Clear PortReset Bit */
253 writel(reg
, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
254 reg
= readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
255 reg
&= ~(1 << 4); /* Clear PortReset Bit */
256 writel(reg
, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
258 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
260 * Enable PCI Express Port0
262 reg
= readl(&cpureg
->ctrl_stat
);
263 reg
|= (1 << 0); /* Set PEX0En Bit */
264 writel(reg
, &cpureg
->ctrl_stat
);
268 #endif /* CONFIG_ARCH_CPU_INIT */
271 * SOC specific misc init
273 #if defined(CONFIG_ARCH_MISC_INIT)
274 int arch_misc_init(void)
278 /*CPU streaming & write allocate */
279 temp
= readfr_extra_feature_reg();
280 temp
&= ~(1 << 28); /* disable wr alloc */
281 writefr_extra_feature_reg(temp
);
283 temp
= readfr_extra_feature_reg();
284 temp
&= ~(1 << 29); /* streaming disabled */
285 writefr_extra_feature_reg(temp
);
287 /* L2Cache settings */
288 temp
= readfr_extra_feature_reg();
289 /* Disable L2C pre fetch - Set bit 24 */
291 /* enable L2C - Set bit 22 */
293 writefr_extra_feature_reg(temp
);
296 /* Change reset vector to address 0x0 */
298 set_cr(temp
& ~CR_V
);
300 /* checks and execute resset to factory event */
305 #endif /* CONFIG_ARCH_MISC_INIT */
308 int cpu_eth_init(bd_t
*bis
)
310 mvgbe_initialize(bis
);
315 #ifdef CONFIG_MVEBU_MMC
316 int board_mmc_init(bd_t
*bis
)
321 #endif /* CONFIG_MVEBU_MMC */