arch/arm/cpu/arm926ejs/mxs/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Groger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Zupke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
  14  *
  15  * Change to support call back into iMX28 bootrom
  16  * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  17  * on behalf of DENX Software Engineering GmbH
  18  *
  19  * SPDX-License-Identifier:     GPL-2.0+
  20  */
  21
  22 #include <asm-offsets.h>
  23 #include <config.h>
  24 #include <common.h>
  25 #include <version.h>
  26
  27 /*
  28  *************************************************************************
  29  *
  30  * Jump vector table as in table 3.1 in [1]
  31  *
  32  *************************************************************************
  33  */
  34
  35
  36 .globl _start
  37 _start:
  38         b       reset
  39         b       undefined_instruction
  40         b       software_interrupt
  41         b       prefetch_abort
  42         b       data_abort
  43         b       not_used
  44         b       irq
  45         b       fiq
  46
  47 /*
  48  * Vector table, located at address 0x20.
  49  * This table allows the code running AFTER SPL, the U-Boot, to install it's
  50  * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
  51  * including it's interrupt vectoring table and the table at 0x0 is still the
  52  * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
  53  * is still used.
  54  */
  55 _vt_reset:
  56         .word   _reset
  57 _vt_undefined_instruction:
  58         .word   _hang
  59 _vt_software_interrupt:
  60         .word   _hang
  61 _vt_prefetch_abort:
  62         .word   _hang
  63 _vt_data_abort:
  64         .word   _hang
  65 _vt_not_used:
  66         .word   _reset
  67 _vt_irq:
  68         .word   _hang
  69 _vt_fiq:
  70         .word   _hang
  71
  72 reset:
  73         ldr     pc, _vt_reset
  74 undefined_instruction:
  75         ldr     pc, _vt_undefined_instruction
  76 software_interrupt:
  77         ldr     pc, _vt_software_interrupt
  78 prefetch_abort:
  79         ldr     pc, _vt_prefetch_abort
  80 data_abort:
  81         ldr     pc, _vt_data_abort
  82 not_used:
  83         ldr     pc, _vt_not_used
  84 irq:
  85         ldr     pc, _vt_irq
  86 fiq:
  87         ldr     pc, _vt_fiq
  88
  89         .balignl 16,0xdeadbeef
  90
  91 /*
  92  *************************************************************************
  93  *
  94  * Startup Code (reset vector)
  95  *
  96  * do important init only if we don't start from memory!
  97  * setup Memory and board specific bits prior to relocation.
  98  * relocate armboot to ram
  99  * setup stack
 100  *
 101  *************************************************************************
 102  */
 103
 104 #ifdef CONFIG_USE_IRQ
 105 /* IRQ stack memory (calculated at run-time) */
 106 .globl IRQ_STACK_START
 107 IRQ_STACK_START:
 108         .word   0x0badc0de
 109
 110 /* IRQ stack memory (calculated at run-time) */
 111 .globl FIQ_STACK_START
 112 FIQ_STACK_START:
 113         .word 0x0badc0de
 114 #endif
 115
 116 /* IRQ stack memory (calculated at run-time) + 8 bytes */
 117 .globl IRQ_STACK_START_IN
 118 IRQ_STACK_START_IN:
 119         .word   0x0badc0de
 120
 121 /*
 122  * the actual reset code
 123  */
 124
 125 _reset:
 126         /*
 127          * If the CPU is configured in "Wait JTAG connection mode", the stack
 128          * pointer is not configured and is zero. This will cause crash when
 129          * trying to push data onto stack right below here. Load the SP and make
 130          * it point to the end of OCRAM if the SP is zero.
 131          */
 132         cmp     sp, #0x00000000
 133         ldreq   sp, =CONFIG_SYS_INIT_SP_ADDR
 134
 135         /*
 136          * Store all registers on old stack pointer, this will allow us later to
 137          * return to the BootROM and let the BootROM load U-Boot into RAM.
 138          *
 139          * WARNING: Register r0 and r1 are used by the BootROM to pass data
 140          *          to the called code. Register r0 will contain arbitrary
 141          *          data that are set in the BootStream. In case this code
 142          *          was started with CALL instruction, register r1 will contain
 143          *          pointer to the return value this function can then set.
 144          *          The code below MUST NOT CHANGE register r0 and r1 !
 145          */
 146         push    {r0-r12,r14}
 147
 148         /* Save control register c1 */
 149         mrc     p15, 0, r2, c1, c0, 0
 150         push    {r2}
 151
 152         /* Set the cpu to SVC32 mode and store old CPSR register content. */
 153         mrs     r2, cpsr
 154         push    {r2}
 155         bic     r2, r2, #0x1f
 156         orr     r2, r2, #0xd3
 157         msr     cpsr, r2
 158
 159         bl      board_init_ll
 160
 161         /* Restore BootROM's CPU mode (especially FIQ). */
 162         pop     {r2}
 163         msr     cpsr,r2
 164
 165         /*
 166          * Restore c1 register. Especially set exception vector location
 167          * back to BootROM space which is required by bootrom for USB boot.
 168          */
 169         pop     {r2}
 170         mcr     p15, 0, r2, c1, c0, 0
 171
 172         pop     {r0-r12,r14}
 173
 174         /*
 175          * In case this code was started by the CALL instruction, the register
 176          * r0 is examined by the BootROM after this code returns. The value in
 177          * r0 must be set to 0 to indicate successful return.
 178          */
 179         mov r0, #0
 180
 181         bx      lr
 182
 183 _hang:
 184 1:
 185         bl      1b                              /* hang and never return */