arch/arm/cpu/arm926ejs/start.S

   1 /*
   2  *  armboot - Startup Code for ARM926EJS CPU-core
   3  *
   4  *  Copyright (c) 2003  Texas Instruments
   5  *
   6  *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7  *
   8  *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9  *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10  *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11  *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12  *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13  *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #include <asm-offsets.h>
  19 #include <config.h>
  20 #include <common.h>
  21 #include <version.h>
  22
  23 /*
  24  *************************************************************************
  25  *
  26  * Startup Code (reset vector)
  27  *
  28  * do important init only if we don't start from memory!
  29  * setup Memory and board specific bits prior to relocation.
  30  * relocate armboot to ram
  31  * setup stack
  32  *
  33  *************************************************************************
  34  */
  35
  36         .globl  reset
  37
  38 reset:
  39         /*
  40          * set the cpu to SVC32 mode
  41          */
  42         mrs     r0,cpsr
  43         bic     r0,r0,#0x1f
  44         orr     r0,r0,#0xd3
  45         msr     cpsr,r0
  46
  47         /*
  48          * we do sys-critical inits only at reboot,
  49          * not when booting from ram!
  50          */
  51 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  52         bl      cpu_init_crit
  53 #endif
  54
  55         bl      _main
  56
  57 /*------------------------------------------------------------------------------*/
  58
  59         .globl  c_runtime_cpu_setup
  60 c_runtime_cpu_setup:
  61
  62         bx      lr
  63
  64 /*
  65  *************************************************************************
  66  *
  67  * CPU_init_critical registers
  68  *
  69  * setup important registers
  70  * setup memory timing
  71  *
  72  *************************************************************************
  73  */
  74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  75 cpu_init_crit:
  76         /*
  77          * flush D cache before disabling it
  78          */
  79         mov     r0, #0
  80 flush_dcache:
  81         mrc     p15, 0, r15, c7, c10, 3
  82         bne     flush_dcache
  83
  84         mcr     p15, 0, r0, c8, c7, 0   /* invalidate TLB */
  85         mcr     p15, 0, r0, c7, c5, 0   /* invalidate I Cache */
  86
  87         /*
  88          * disable MMU and D cache
  89          * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
  90          */
  91         mrc     p15, 0, r0, c1, c0, 0
  92         bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
  93         bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
  94 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  95         orr     r0, r0, #0x00002000     /* set bit 13 (--V- ----) */
  96 #else
  97         bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
  98 #endif
  99         orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
 100 #ifndef CONFIG_SYS_ICACHE_OFF
 101         orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
 102 #endif
 103         mcr     p15, 0, r0, c1, c0, 0
 104
 105         /*
 106          * Go setup Memory and board specific bits prior to relocation.
 107          */
 108         mov     ip, lr          /* perserve link reg across call */
 109         bl      lowlevel_init   /* go setup pll,mux,memory */
 110         mov     lr, ip          /* restore link */
 111         mov     pc, lr          /* back to my caller */
 112 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */