arch/arm/cpu/arm_cortexa8/omap3/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2008
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Initial Code by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Syed Mohammed Khasim <khasim@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/arch/mem.h>
  33 #include <asm/arch/clocks_omap3.h>
  34
  35 _TEXT_BASE:
  36         .word   TEXT_BASE       /* sdram load addr from config.mk */
  37
  38 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
  39 /**************************************************************************
  40  * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  41  * R1 = SRAM destination address.
  42  *************************************************************************/
  43 .global cpy_clk_code
  44  cpy_clk_code:
  45         /* Copy DPLL code into SRAM */
  46         adr     r0, go_to_speed         /* get addr of clock setting code */
  47         mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
  48         mov     r1, r1                  /* r1 <- dest address (passed in) */
  49         add     r2, r2, r0              /* r2 <- source end address */
  50 next2:
  51         ldmia   r0!, {r3 - r10}         /* copy from source address [r0] */
  52         stmia   r1!, {r3 - r10}         /* copy to   target address [r1] */
  53         cmp     r0, r2                  /* until source end address [r2] */
  54         bne     next2
  55         mov     pc, lr                  /* back to caller */
  56
  57 /* ***************************************************************************
  58  *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
  59  *               -executed from SRAM.
  60  *  R0 = CM_CLKEN_PLL-bypass value
  61  *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
  62  *  R2 = CM_CLKSEL_CORE-divider values
  63  *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
  64  *
  65  *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
  66  *        confused.  A reset of the controller gets it back.  Taking away its
  67  *        L3 when its not in self refresh seems bad for it.  Normally, this
  68  *        code runs from flash before SDR is init so that should be ok.
  69  ****************************************************************************/
  70 .global go_to_speed
  71  go_to_speed:
  72         stmfd sp!, {r4 - r6}
  73
  74         /* move into fast relock bypass */
  75         ldr     r4, pll_ctl_add
  76         str     r0, [r4]
  77 wait1:
  78         ldr     r5, [r3]                /* get status */
  79         and     r5, r5, #0x1            /* isolate core status */
  80         cmp     r5, #0x1                /* still locked? */
  81         beq     wait1                   /* if lock, loop */
  82
  83         /* set new dpll dividers _after_ in bypass */
  84         ldr     r5, pll_div_add1
  85         str     r1, [r5]                /* set m, n, m2 */
  86         ldr     r5, pll_div_add2
  87         str     r2, [r5]                /* set l3/l4/.. dividers*/
  88         ldr     r5, pll_div_add3        /* wkup */
  89         ldr     r2, pll_div_val3        /* rsm val */
  90         str     r2, [r5]
  91         ldr     r5, pll_div_add4        /* gfx */
  92         ldr     r2, pll_div_val4
  93         str     r2, [r5]
  94         ldr     r5, pll_div_add5        /* emu */
  95         ldr     r2, pll_div_val5
  96         str     r2, [r5]
  97
  98         /* now prepare GPMC (flash) for new dpll speed */
  99         /* flash needs to be stable when we jump back to it */
 100         ldr     r5, flash_cfg3_addr
 101         ldr     r2, flash_cfg3_val
 102         str     r2, [r5]
 103         ldr     r5, flash_cfg4_addr
 104         ldr     r2, flash_cfg4_val
 105         str     r2, [r5]
 106         ldr     r5, flash_cfg5_addr
 107         ldr     r2, flash_cfg5_val
 108         str     r2, [r5]
 109         ldr     r5, flash_cfg1_addr
 110         ldr     r2, [r5]
 111         orr     r2, r2, #0x3            /* up gpmc divider */
 112         str     r2, [r5]
 113
 114         /* lock DPLL3 and wait a bit */
 115         orr     r0, r0, #0x7    /* set up for lock mode */
 116         str     r0, [r4]        /* lock */
 117         nop                     /* ARM slow at this point working at sys_clk */
 118         nop
 119         nop
 120         nop
 121 wait2:
 122         ldr     r5, [r3]        /* get status */
 123         and     r5, r5, #0x1    /* isolate core status */
 124         cmp     r5, #0x1        /* still locked? */
 125         bne     wait2           /* if lock, loop */
 126         nop
 127         nop
 128         nop
 129         nop
 130         ldmfd   sp!, {r4 - r6}
 131         mov     pc, lr          /* back to caller, locked */
 132
 133 _go_to_speed: .word go_to_speed
 134
 135 /* these constants need to be close for PIC code */
 136 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
 137 flash_cfg1_addr:
 138         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
 139 flash_cfg3_addr:
 140         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
 141 flash_cfg3_val:
 142         .word STNOR_GPMC_CONFIG3
 143 flash_cfg4_addr:
 144         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
 145 flash_cfg4_val:
 146         .word STNOR_GPMC_CONFIG4
 147 flash_cfg5_val:
 148         .word STNOR_GPMC_CONFIG5
 149 flash_cfg5_addr:
 150         .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
 151 pll_ctl_add:
 152         .word CM_CLKEN_PLL
 153 pll_div_add1:
 154         .word CM_CLKSEL1_PLL
 155 pll_div_add2:
 156         .word CM_CLKSEL_CORE
 157 pll_div_add3:
 158         .word CM_CLKSEL_WKUP
 159 pll_div_val3:
 160         .word (WKUP_RSM << 1)
 161 pll_div_add4:
 162         .word CM_CLKSEL_GFX
 163 pll_div_val4:
 164         .word (GFX_DIV << 0)
 165 pll_div_add5:
 166         .word CM_CLKSEL1_EMU
 167 pll_div_val5:
 168         .word CLSEL1_EMU_VAL
 169
 170 #endif
 171
 172 .globl lowlevel_init
 173 lowlevel_init:
 174         ldr     sp, SRAM_STACK
 175         str     ip, [sp]        /* stash old link register */
 176         mov     ip, lr          /* save link reg across call */
 177         bl      s_init          /* go setup pll, mux, memory */
 178         ldr     ip, [sp]        /* restore save ip */
 179         mov     lr, ip          /* restore link reg */
 180
 181         /* back to arch calling code */
 182         mov     pc, lr
 183
 184         /* the literal pools origin */
 185         .ltorg
 186
 187 REG_CONTROL_STATUS:
 188         .word CONTROL_STATUS
 189 SRAM_STACK:
 190         .word LOW_LEVEL_SRAM_STACK
 191
 192 /* DPLL(1-4) PARAM TABLES */
 193
 194 /*
 195  * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
 196  * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
 197  * The values are defined for all possible sysclk and for ES1 and ES2.
 198  */
 199
 200 mpu_dpll_param:
 201 /* 12MHz */
 202 /* ES1 */
 203 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
 204 /* ES2 */
 205 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
 206 /* 3410 */
 207 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
 208
 209 /* 13MHz */
 210 /* ES1 */
 211 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
 212 /* ES2 */
 213 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
 214 /* 3410 */
 215 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
 216
 217 /* 19.2MHz */
 218 /* ES1 */
 219 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
 220 /* ES2 */
 221 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
 222 /* 3410 */
 223 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
 224
 225 /* 26MHz */
 226 /* ES1 */
 227 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
 228 /* ES2 */
 229 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
 230 /* 3410 */
 231 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
 232
 233 /* 38.4MHz */
 234 /* ES1 */
 235 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
 236 /* ES2 */
 237 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
 238 /* 3410 */
 239 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
 240
 241
 242 .globl get_mpu_dpll_param
 243 get_mpu_dpll_param:
 244         adr     r0, mpu_dpll_param
 245         mov     pc, lr
 246
 247 iva_dpll_param:
 248 /* 12MHz */
 249 /* ES1 */
 250 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
 251 /* ES2 */
 252 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
 253 /* 3410 */
 254 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
 255
 256 /* 13MHz */
 257 /* ES1 */
 258 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
 259 /* ES2 */
 260 .word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
 261 /* 3410 */
 262 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
 263
 264 /* 19.2MHz */
 265 /* ES1 */
 266 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
 267 /* ES2 */
 268 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
 269 /* 3410 */
 270 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
 271
 272 /* 26MHz */
 273 /* ES1 */
 274 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
 275 /* ES2 */
 276 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
 277 /* 3410 */
 278 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
 279
 280 /* 38.4MHz */
 281 /* ES1 */
 282 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
 283 /* ES2 */
 284 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
 285 /* 3410 */
 286 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
 287
 288
 289 .globl get_iva_dpll_param
 290 get_iva_dpll_param:
 291         adr     r0, iva_dpll_param
 292         mov     pc, lr
 293
 294 /* Core DPLL targets for L3 at 166 & L133 */
 295 core_dpll_param:
 296 /* 12MHz */
 297 /* ES1 */
 298 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
 299 /* ES2 */
 300 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 301 /* 3410 */
 302 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
 303
 304 /* 13MHz */
 305 /* ES1 */
 306 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
 307 /* ES2 */
 308 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 309 /* 3410 */
 310 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
 311
 312 /* 19.2MHz */
 313 /* ES1 */
 314 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
 315 /* ES2 */
 316 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 317 /* 3410 */
 318 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
 319
 320 /* 26MHz */
 321 /* ES1 */
 322 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
 323 /* ES2 */
 324 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 325 /* 3410 */
 326 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
 327
 328 /* 38.4MHz */
 329 /* ES1 */
 330 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
 331 /* ES2 */
 332 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 333 /* 3410 */
 334 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
 335
 336 .globl get_core_dpll_param
 337 get_core_dpll_param:
 338         adr     r0, core_dpll_param
 339         mov     pc, lr
 340
 341 /* PER DPLL values are same for both ES1 and ES2 */
 342 per_dpll_param:
 343 /* 12MHz */
 344 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
 345
 346 /* 13MHz */
 347 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
 348
 349 /* 19.2MHz */
 350 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
 351
 352 /* 26MHz */
 353 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
 354
 355 /* 38.4MHz */
 356 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
 357
 358 .globl get_per_dpll_param
 359 get_per_dpll_param:
 360         adr     r0, per_dpll_param
 361         mov     pc, lr