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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/am33xx/clock_am33xx.c
4 * clocks for AM33XX based boards
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/hardware.h>
25 #define PRCM_MOD_EN 0x2
26 #define PRCM_FORCE_WAKEUP 0x2
27 #define PRCM_FUNCTL 0x0
29 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
30 #define PRCM_L3_GCLK_ACTIVITY BIT(4)
32 #define PLL_BYPASS_MODE 0x4
33 #define ST_MN_BYPASS 0x00000100
34 #define ST_DPLL_CLK 0x00000001
35 #define CLK_SEL_MASK 0x7ffff
36 #define CLK_DIV_MASK 0x1f
37 #define CLK_DIV2_MASK 0x7f
38 #define CLK_SEL_SHIFT 0x8
39 #define CLK_MODE_SEL 0x7
40 #define CLK_MODE_MASK 0xfffffff8
41 #define CLK_DIV_SEL 0xFFFFFFE0
42 #define CPGMAC0_IDLE 0x30000
43 #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
45 #define OSC (V_OSCK/1000000)
47 #define MPUPLL_M CONFIG_SYS_MPUCLK
48 #define MPUPLL_N (OSC-1)
51 /* Core PLL Fdll = 1 GHZ, */
52 #define COREPLL_M 1000
53 #define COREPLL_N (OSC-1)
55 #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
56 #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
57 #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
60 * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
61 * frequency needs to be set to 960 MHZ. Hence,
62 * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
65 #define PERPLL_N (OSC-1)
68 /* DDR Freq is 266 MHZ for now */
69 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
71 #define DDRPLL_N (OSC-1)
74 const struct cm_perpll
*cmper
= (struct cm_perpll
*)CM_PER
;
75 const struct cm_wkuppll
*cmwkup
= (struct cm_wkuppll
*)CM_WKUP
;
76 const struct cm_dpll
*cmdpll
= (struct cm_dpll
*)CM_DPLL
;
77 const struct cm_rtc
*cmrtc
= (struct cm_rtc
*)CM_RTC
;
79 static void enable_interface_clocks(void)
81 /* Enable all the Interconnect Modules */
82 writel(PRCM_MOD_EN
, &cmper
->l3clkctrl
);
83 while (readl(&cmper
->l3clkctrl
) != PRCM_MOD_EN
)
86 writel(PRCM_MOD_EN
, &cmper
->l4lsclkctrl
);
87 while (readl(&cmper
->l4lsclkctrl
) != PRCM_MOD_EN
)
90 writel(PRCM_MOD_EN
, &cmper
->l4fwclkctrl
);
91 while (readl(&cmper
->l4fwclkctrl
) != PRCM_MOD_EN
)
94 writel(PRCM_MOD_EN
, &cmwkup
->wkl4wkclkctrl
);
95 while (readl(&cmwkup
->wkl4wkclkctrl
) != PRCM_MOD_EN
)
98 writel(PRCM_MOD_EN
, &cmper
->l3instrclkctrl
);
99 while (readl(&cmper
->l3instrclkctrl
) != PRCM_MOD_EN
)
102 writel(PRCM_MOD_EN
, &cmper
->l4hsclkctrl
);
103 while (readl(&cmper
->l4hsclkctrl
) != PRCM_MOD_EN
)
106 writel(PRCM_MOD_EN
, &cmwkup
->wkgpio0clkctrl
);
107 while (readl(&cmwkup
->wkgpio0clkctrl
) != PRCM_MOD_EN
)
112 * Force power domain wake up transition
113 * Ensure that the corresponding interface clock is active before
114 * using the peripheral
116 static void power_domain_wkup_transition(void)
118 writel(PRCM_FORCE_WAKEUP
, &cmper
->l3clkstctrl
);
119 writel(PRCM_FORCE_WAKEUP
, &cmper
->l4lsclkstctrl
);
120 writel(PRCM_FORCE_WAKEUP
, &cmwkup
->wkclkstctrl
);
121 writel(PRCM_FORCE_WAKEUP
, &cmper
->l4fwclkstctrl
);
122 writel(PRCM_FORCE_WAKEUP
, &cmper
->l3sclkstctrl
);
126 * Enable the peripheral clock for required peripherals
128 static void enable_per_clocks(void)
130 /* Enable the control module though RBL would have done it*/
131 writel(PRCM_MOD_EN
, &cmwkup
->wkctrlclkctrl
);
132 while (readl(&cmwkup
->wkctrlclkctrl
) != PRCM_MOD_EN
)
135 /* Enable the module clock */
136 writel(PRCM_MOD_EN
, &cmper
->timer2clkctrl
);
137 while (readl(&cmper
->timer2clkctrl
) != PRCM_MOD_EN
)
140 /* Select the Master osc 24 MHZ as Timer2 clock source */
141 writel(0x1, &cmdpll
->clktimer2clk
);
144 writel(PRCM_MOD_EN
, &cmwkup
->wkup_uart0ctrl
);
145 while (readl(&cmwkup
->wkup_uart0ctrl
) != PRCM_MOD_EN
)
149 #ifdef CONFIG_SERIAL2
150 writel(PRCM_MOD_EN
, &cmper
->uart1clkctrl
);
151 while (readl(&cmper
->uart1clkctrl
) != PRCM_MOD_EN
)
153 #endif /* CONFIG_SERIAL2 */
156 #ifdef CONFIG_SERIAL3
157 writel(PRCM_MOD_EN
, &cmper
->uart2clkctrl
);
158 while (readl(&cmper
->uart2clkctrl
) != PRCM_MOD_EN
)
160 #endif /* CONFIG_SERIAL3 */
163 #ifdef CONFIG_SERIAL4
164 writel(PRCM_MOD_EN
, &cmper
->uart3clkctrl
);
165 while (readl(&cmper
->uart3clkctrl
) != PRCM_MOD_EN
)
167 #endif /* CONFIG_SERIAL4 */
170 #ifdef CONFIG_SERIAL5
171 writel(PRCM_MOD_EN
, &cmper
->uart4clkctrl
);
172 while (readl(&cmper
->uart4clkctrl
) != PRCM_MOD_EN
)
174 #endif /* CONFIG_SERIAL5 */
177 #ifdef CONFIG_SERIAL6
178 writel(PRCM_MOD_EN
, &cmper
->uart5clkctrl
);
179 while (readl(&cmper
->uart5clkctrl
) != PRCM_MOD_EN
)
181 #endif /* CONFIG_SERIAL6 */
184 writel(PRCM_MOD_EN
, &cmper
->gpmcclkctrl
);
185 while (readl(&cmper
->gpmcclkctrl
) != PRCM_MOD_EN
)
189 writel(PRCM_MOD_EN
, &cmper
->elmclkctrl
);
190 while (readl(&cmper
->elmclkctrl
) != PRCM_MOD_EN
)
194 writel(PRCM_MOD_EN
, &cmper
->mmc0clkctrl
);
195 while (readl(&cmper
->mmc0clkctrl
) != PRCM_MOD_EN
)
199 writel(PRCM_MOD_EN
, &cmwkup
->wkup_i2c0ctrl
);
200 while (readl(&cmwkup
->wkup_i2c0ctrl
) != PRCM_MOD_EN
)
204 writel(PRCM_MOD_EN
, &cmper
->gpio1clkctrl
);
205 while (readl(&cmper
->gpio1clkctrl
) != PRCM_MOD_EN
)
209 writel(PRCM_MOD_EN
, &cmper
->gpio2clkctrl
);
210 while (readl(&cmper
->gpio2clkctrl
) != PRCM_MOD_EN
)
214 writel(PRCM_MOD_EN
, &cmper
->gpio3clkctrl
);
215 while (readl(&cmper
->gpio3clkctrl
) != PRCM_MOD_EN
)
219 writel(PRCM_MOD_EN
, &cmper
->i2c1clkctrl
);
220 while (readl(&cmper
->i2c1clkctrl
) != PRCM_MOD_EN
)
224 writel(PRCM_MOD_EN
, &cmper
->cpgmac0clkctrl
);
225 while ((readl(&cmper
->cpgmac0clkctrl
) & CPGMAC0_IDLE
) != PRCM_FUNCTL
)
229 writel(PRCM_MOD_EN
, &cmper
->spi0clkctrl
);
230 while (readl(&cmper
->spi0clkctrl
) != PRCM_MOD_EN
)
234 writel(PRCM_MOD_EN
, &cmrtc
->rtcclkctrl
);
235 while (readl(&cmrtc
->rtcclkctrl
) != PRCM_MOD_EN
)
239 writel(PRCM_MOD_EN
, &cmper
->usb0clkctrl
);
240 while (readl(&cmper
->usb0clkctrl
) != PRCM_MOD_EN
)
244 static void mpu_pll_config(void)
246 u32 clkmode
, clksel
, div_m2
;
248 clkmode
= readl(&cmwkup
->clkmoddpllmpu
);
249 clksel
= readl(&cmwkup
->clkseldpllmpu
);
250 div_m2
= readl(&cmwkup
->divm2dpllmpu
);
252 /* Set the PLL to bypass Mode */
253 writel(PLL_BYPASS_MODE
, &cmwkup
->clkmoddpllmpu
);
254 while (readl(&cmwkup
->idlestdpllmpu
) != ST_MN_BYPASS
)
257 clksel
= clksel
& (~CLK_SEL_MASK
);
258 clksel
= clksel
| ((MPUPLL_M
<< CLK_SEL_SHIFT
) | MPUPLL_N
);
259 writel(clksel
, &cmwkup
->clkseldpllmpu
);
261 div_m2
= div_m2
& ~CLK_DIV_MASK
;
262 div_m2
= div_m2
| MPUPLL_M2
;
263 writel(div_m2
, &cmwkup
->divm2dpllmpu
);
265 clkmode
= clkmode
| CLK_MODE_SEL
;
266 writel(clkmode
, &cmwkup
->clkmoddpllmpu
);
268 while (readl(&cmwkup
->idlestdpllmpu
) != ST_DPLL_CLK
)
272 static void core_pll_config(void)
274 u32 clkmode
, clksel
, div_m4
, div_m5
, div_m6
;
276 clkmode
= readl(&cmwkup
->clkmoddpllcore
);
277 clksel
= readl(&cmwkup
->clkseldpllcore
);
278 div_m4
= readl(&cmwkup
->divm4dpllcore
);
279 div_m5
= readl(&cmwkup
->divm5dpllcore
);
280 div_m6
= readl(&cmwkup
->divm6dpllcore
);
282 /* Set the PLL to bypass Mode */
283 writel(PLL_BYPASS_MODE
, &cmwkup
->clkmoddpllcore
);
285 while (readl(&cmwkup
->idlestdpllcore
) != ST_MN_BYPASS
)
288 clksel
= clksel
& (~CLK_SEL_MASK
);
289 clksel
= clksel
| ((COREPLL_M
<< CLK_SEL_SHIFT
) | COREPLL_N
);
290 writel(clksel
, &cmwkup
->clkseldpllcore
);
292 div_m4
= div_m4
& ~CLK_DIV_MASK
;
293 div_m4
= div_m4
| COREPLL_M4
;
294 writel(div_m4
, &cmwkup
->divm4dpllcore
);
296 div_m5
= div_m5
& ~CLK_DIV_MASK
;
297 div_m5
= div_m5
| COREPLL_M5
;
298 writel(div_m5
, &cmwkup
->divm5dpllcore
);
300 div_m6
= div_m6
& ~CLK_DIV_MASK
;
301 div_m6
= div_m6
| COREPLL_M6
;
302 writel(div_m6
, &cmwkup
->divm6dpllcore
);
304 clkmode
= clkmode
| CLK_MODE_SEL
;
305 writel(clkmode
, &cmwkup
->clkmoddpllcore
);
307 while (readl(&cmwkup
->idlestdpllcore
) != ST_DPLL_CLK
)
311 static void per_pll_config(void)
313 u32 clkmode
, clksel
, div_m2
;
315 clkmode
= readl(&cmwkup
->clkmoddpllper
);
316 clksel
= readl(&cmwkup
->clkseldpllper
);
317 div_m2
= readl(&cmwkup
->divm2dpllper
);
319 /* Set the PLL to bypass Mode */
320 writel(PLL_BYPASS_MODE
, &cmwkup
->clkmoddpllper
);
322 while (readl(&cmwkup
->idlestdpllper
) != ST_MN_BYPASS
)
325 clksel
= clksel
& (~CLK_SEL_MASK
);
326 clksel
= clksel
| ((PERPLL_M
<< CLK_SEL_SHIFT
) | PERPLL_N
);
327 writel(clksel
, &cmwkup
->clkseldpllper
);
329 div_m2
= div_m2
& ~CLK_DIV2_MASK
;
330 div_m2
= div_m2
| PERPLL_M2
;
331 writel(div_m2
, &cmwkup
->divm2dpllper
);
333 clkmode
= clkmode
| CLK_MODE_SEL
;
334 writel(clkmode
, &cmwkup
->clkmoddpllper
);
336 while (readl(&cmwkup
->idlestdpllper
) != ST_DPLL_CLK
)
339 writel(DPLL_CLKDCOLDO_GATE_CTRL
, &cmwkup
->clkdcoldodpllper
);
342 void ddr_pll_config(unsigned int ddrpll_m
)
344 u32 clkmode
, clksel
, div_m2
;
346 clkmode
= readl(&cmwkup
->clkmoddpllddr
);
347 clksel
= readl(&cmwkup
->clkseldpllddr
);
348 div_m2
= readl(&cmwkup
->divm2dpllddr
);
350 /* Set the PLL to bypass Mode */
351 clkmode
= (clkmode
& CLK_MODE_MASK
) | PLL_BYPASS_MODE
;
352 writel(clkmode
, &cmwkup
->clkmoddpllddr
);
354 /* Wait till bypass mode is enabled */
355 while ((readl(&cmwkup
->idlestdpllddr
) & ST_MN_BYPASS
)
359 clksel
= clksel
& (~CLK_SEL_MASK
);
360 clksel
= clksel
| ((ddrpll_m
<< CLK_SEL_SHIFT
) | DDRPLL_N
);
361 writel(clksel
, &cmwkup
->clkseldpllddr
);
363 div_m2
= div_m2
& CLK_DIV_SEL
;
364 div_m2
= div_m2
| DDRPLL_M2
;
365 writel(div_m2
, &cmwkup
->divm2dpllddr
);
367 clkmode
= (clkmode
& CLK_MODE_MASK
) | CLK_MODE_SEL
;
368 writel(clkmode
, &cmwkup
->clkmoddpllddr
);
370 /* Wait till dpll is locked */
371 while ((readl(&cmwkup
->idlestdpllddr
) & ST_DPLL_CLK
) != ST_DPLL_CLK
)
375 void enable_emif_clocks(void)
377 /* Enable the EMIF_FW Functional clock */
378 writel(PRCM_MOD_EN
, &cmper
->emiffwclkctrl
);
379 /* Enable EMIF0 Clock */
380 writel(PRCM_MOD_EN
, &cmper
->emifclkctrl
);
381 /* Poll if module is functional */
382 while ((readl(&cmper
->emifclkctrl
)) != PRCM_MOD_EN
)
387 * Configure the PLL/PRCM for necessary peripherals
395 /* Enable the required interconnect clocks */
396 enable_interface_clocks();
398 /* Power domain wake up transition */
399 power_domain_wkup_transition();
401 /* Enable the required peripherals */