arch/arm/cpu/armv7/am33xx/clock_ti814x.c

   1 /*
   2  * clock_ti814x.c
   3  *
   4  * Clocks for TI814X based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/io.h>
  16
  17 /* PRCM */
  18 #define PRCM_MOD_EN             0x2
  19
  20 /* CLK_SRC */
  21 #define OSC_SRC0                0
  22 #define OSC_SRC1                1
  23
  24 #define L3_OSC_SRC              OSC_SRC0
  25
  26 #define OSC_0_FREQ              20
  27
  28 #define DCO_HS2_MIN             500
  29 #define DCO_HS2_MAX             1000
  30 #define DCO_HS1_MIN             1000
  31 #define DCO_HS1_MAX             2000
  32
  33 #define SELFREQDCO_HS2          0x00000801
  34 #define SELFREQDCO_HS1          0x00001001
  35
  36 #define MPU_N                   0x1
  37 #define MPU_M                   0x3C
  38 #define MPU_M2                  1
  39 #define MPU_CLKCTRL             0x1
  40
  41 #define L3_N                    19
  42 #define L3_M                    880
  43 #define L3_M2                   4
  44 #define L3_CLKCTRL              0x801
  45
  46 #define DDR_N                   19
  47 #define DDR_M                   666
  48 #define DDR_M2                  2
  49 #define DDR_CLKCTRL             0x801
  50
  51 /* ADPLLJ register values */
  52 #define ADPLLJ_CLKCTRL_HS2      0x00000801 /* HS2 mode, TINT2 = 1 */
  53 #define ADPLLJ_CLKCTRL_HS1      0x00001001 /* HS1 mode, TINT2 = 1 */
  54 #define ADPLLJ_CLKCTRL_CLKDCOLDOEN      (1 << 29)
  55 #define ADPLLJ_CLKCTRL_IDLE             (1 << 23)
  56 #define ADPLLJ_CLKCTRL_CLKOUTEN         (1 << 20)
  57 #define ADPLLJ_CLKCTRL_CLKOUTLDOEN      (1 << 19)
  58 #define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ   (1 << 17)
  59 #define ADPLLJ_CLKCTRL_LPMODE           (1 << 12)
  60 #define ADPLLJ_CLKCTRL_DRIFTGUARDIAN    (1 << 11)
  61 #define ADPLLJ_CLKCTRL_REGM4XEN         (1 << 10)
  62 #define ADPLLJ_CLKCTRL_TINITZ           (1 << 0)
  63 #define ADPLLJ_CLKCTRL_CLKDCO           (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
  64                                          ADPLLJ_CLKCTRL_CLKOUTEN | \
  65                                          ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
  66                                          ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
  67
  68 #define ADPLLJ_STATUS_PHASELOCK         (1 << 10)
  69 #define ADPLLJ_STATUS_FREQLOCK          (1 << 9)
  70 #define ADPLLJ_STATUS_PHSFRQLOCK        (ADPLLJ_STATUS_PHASELOCK | \
  71                                          ADPLLJ_STATUS_FREQLOCK)
  72 #define ADPLLJ_STATUS_BYPASSACK         (1 << 8)
  73 #define ADPLLJ_STATUS_BYPASS            (1 << 0)
  74 #define ADPLLJ_STATUS_BYPASSANDACK      (ADPLLJ_STATUS_BYPASSACK | \
  75                                          ADPLLJ_STATUS_BYPASS)
  76
  77 #define ADPLLJ_TENABLE_ENB              (1 << 0)
  78 #define ADPLLJ_TENABLEDIV_ENB           (1 << 0)
  79
  80 #define ADPLLJ_M2NDIV_M2SHIFT           16
  81
  82 #define MPU_PLL_BASE                    (PLL_SUBSYS_BASE + 0x048)
  83 #define L3_PLL_BASE                     (PLL_SUBSYS_BASE + 0x110)
  84 #define DDR_PLL_BASE                    (PLL_SUBSYS_BASE + 0x290)
  85
  86 struct ad_pll {
  87         unsigned int pwrctrl;
  88         unsigned int clkctrl;
  89         unsigned int tenable;
  90         unsigned int tenablediv;
  91         unsigned int m2ndiv;
  92         unsigned int mn2div;
  93         unsigned int fracdiv;
  94         unsigned int bwctrl;
  95         unsigned int fracctrl;
  96         unsigned int status;
  97         unsigned int m3div;
  98         unsigned int rampctrl;
  99 };
 100
 101 #define OSC_SRC_CTRL                    (PLL_SUBSYS_BASE + 0x2C0)
 102
 103 /* PRCM */
 104 #define ENET_CLKCTRL_CMPL               0x30000
 105
 106 #define CM_DEFAULT_BASE                 (PRCM_BASE + 0x0500)
 107
 108 struct cm_def {
 109         unsigned int resv0[2];
 110         unsigned int l3fastclkstctrl;
 111         unsigned int resv1[1];
 112         unsigned int pciclkstctrl;
 113         unsigned int resv2[1];
 114         unsigned int ducaticlkstctrl;
 115         unsigned int resv3[1];
 116         unsigned int emif0clkctrl;
 117         unsigned int emif1clkctrl;
 118         unsigned int dmmclkctrl;
 119         unsigned int fwclkctrl;
 120         unsigned int resv4[10];
 121         unsigned int usbclkctrl;
 122         unsigned int resv5[1];
 123         unsigned int sataclkctrl;
 124         unsigned int resv6[4];
 125         unsigned int ducaticlkctrl;
 126         unsigned int pciclkctrl;
 127 };
 128
 129 #define CM_ALWON_BASE                   (PRCM_BASE + 0x1400)
 130
 131 struct cm_alwon {
 132         unsigned int l3slowclkstctrl;
 133         unsigned int ethclkstctrl;
 134         unsigned int l3medclkstctrl;
 135         unsigned int mmu_clkstctrl;
 136         unsigned int mmucfg_clkstctrl;
 137         unsigned int ocmc0clkstctrl;
 138         unsigned int vcpclkstctrl;
 139         unsigned int mpuclkstctrl;
 140         unsigned int sysclk4clkstctrl;
 141         unsigned int sysclk5clkstctrl;
 142         unsigned int sysclk6clkstctrl;
 143         unsigned int rtcclkstctrl;
 144         unsigned int l3fastclkstctrl;
 145         unsigned int resv0[67];
 146         unsigned int mcasp0clkctrl;
 147         unsigned int mcasp1clkctrl;
 148         unsigned int mcasp2clkctrl;
 149         unsigned int mcbspclkctrl;
 150         unsigned int uart0clkctrl;
 151         unsigned int uart1clkctrl;
 152         unsigned int uart2clkctrl;
 153         unsigned int gpio0clkctrl;
 154         unsigned int gpio1clkctrl;
 155         unsigned int i2c0clkctrl;
 156         unsigned int i2c1clkctrl;
 157         unsigned int mcasp345clkctrl;
 158         unsigned int atlclkctrl;
 159         unsigned int mlbclkctrl;
 160         unsigned int pataclkctrl;
 161         unsigned int resv1[1];
 162         unsigned int uart3clkctrl;
 163         unsigned int uart4clkctrl;
 164         unsigned int uart5clkctrl;
 165         unsigned int wdtimerclkctrl;
 166         unsigned int spiclkctrl;
 167         unsigned int mailboxclkctrl;
 168         unsigned int spinboxclkctrl;
 169         unsigned int mmudataclkctrl;
 170         unsigned int resv2[2];
 171         unsigned int mmucfgclkctrl;
 172         unsigned int resv3[2];
 173         unsigned int ocmc0clkctrl;
 174         unsigned int vcpclkctrl;
 175         unsigned int resv4[2];
 176         unsigned int controlclkctrl;
 177         unsigned int resv5[2];
 178         unsigned int gpmcclkctrl;
 179         unsigned int ethernet0clkctrl;
 180         unsigned int ethernet1clkctrl;
 181         unsigned int mpuclkctrl;
 182         unsigned int debugssclkctrl;
 183         unsigned int l3clkctrl;
 184         unsigned int l4hsclkctrl;
 185         unsigned int l4lsclkctrl;
 186         unsigned int rtcclkctrl;
 187         unsigned int tpccclkctrl;
 188         unsigned int tptc0clkctrl;
 189         unsigned int tptc1clkctrl;
 190         unsigned int tptc2clkctrl;
 191         unsigned int tptc3clkctrl;
 192         unsigned int resv7[4];
 193         unsigned int dcan01clkctrl;
 194         unsigned int mmchs0clkctrl;
 195         unsigned int mmchs1clkctrl;
 196         unsigned int mmchs2clkctrl;
 197         unsigned int custefuseclkctrl;
 198 };
 199
 200 #define SATA_PLL_BASE                   (CTRL_BASE + 0x0720)
 201
 202 struct sata_pll {
 203         unsigned int pllcfg0;
 204         unsigned int pllcfg1;
 205         unsigned int pllcfg2;
 206         unsigned int pllcfg3;
 207         unsigned int pllcfg4;
 208         unsigned int pllstatus;
 209         unsigned int rxstatus;
 210         unsigned int txstatus;
 211         unsigned int testcfg;
 212 };
 213
 214 #define SEL_IN_FREQ             (0x1 << 31)
 215 #define DIGCLRZ                 (0x1 << 30)
 216 #define ENDIGLDO                (0x1 << 4)
 217 #define APLL_CP_CURR            (0x1 << 3)
 218 #define ENBGSC_REF              (0x1 << 2)
 219 #define ENPLLLDO                (0x1 << 1)
 220 #define ENPLL                   (0x1 << 0)
 221
 222 #define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
 223 #define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
 224 #define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
 225 #define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
 226                         ENPLLLDO | ENPLL)
 227
 228 #define PLL_LOCK                (0x1 << 0)
 229
 230 #define ENSATAMODE              (0x1 << 31)
 231 #define PLLREFSEL               (0x1 << 30)
 232 #define MDIVINT                 (0x4b << 18)
 233 #define EN_CLKAUX               (0x1 << 5)
 234 #define EN_CLK125M              (0x1 << 4)
 235 #define EN_CLK100M              (0x1 << 3)
 236 #define EN_CLK50M               (0x1 << 2)
 237
 238 #define SATA_PLLCFG1 (ENSATAMODE |      \
 239                       PLLREFSEL |       \
 240                       MDIVINT |         \
 241                       EN_CLKAUX |       \
 242                       EN_CLK125M |      \
 243                       EN_CLK100M |      \
 244                       EN_CLK50M)
 245
 246 #define DIGLDO_EN_CAPLESSMODE   (0x1 << 22)
 247 #define PLLDO_EN_LDO_STABLE     (0x1 << 11)
 248 #define PLLDO_EN_BUF_CUR        (0x1 << 7)
 249 #define PLLDO_EN_LP             (0x1 << 6)
 250 #define PLLDO_CTRL_TRIM_1_4V    (0x10 << 1)
 251
 252 #define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE |   \
 253                       PLLDO_EN_LDO_STABLE |     \
 254                       PLLDO_EN_BUF_CUR |        \
 255                       PLLDO_EN_LP |             \
 256                       PLLDO_CTRL_TRIM_1_4V)
 257
 258 const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
 259 const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
 260 const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
 261
 262 /*
 263  * Enable the peripheral clock for required peripherals
 264  */
 265 static void enable_per_clocks(void)
 266 {
 267         /* UART0 */
 268         writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
 269         while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
 270                 ;
 271
 272         /* HSMMC1 */
 273         writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
 274         while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
 275                 ;
 276
 277         /* Ethernet */
 278         writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
 279         writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
 280         while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
 281                 ;
 282         writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
 283         while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
 284                 ;
 285 }
 286
 287 /*
 288  * select the HS1 or HS2 for DCO Freq
 289  * return : CLKCTRL
 290  */
 291 static u32 pll_dco_freq_sel(u32 clkout_dco)
 292 {
 293         if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
 294                 return SELFREQDCO_HS2;
 295         else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
 296                 return SELFREQDCO_HS1;
 297         else
 298                 return -1;
 299 }
 300
 301 /*
 302  * select the sigma delta config
 303  * return: sigma delta val
 304  */
 305 static u32 pll_sigma_delta_val(u32 clkout_dco)
 306 {
 307         u32 sig_val = 0;
 308         float frac_div;
 309
 310         frac_div = (float) clkout_dco / 250;
 311         frac_div = frac_div + 0.90;
 312         sig_val = (int)frac_div;
 313         sig_val = sig_val << 24;
 314
 315         return sig_val;
 316 }
 317
 318 /*
 319  * configure individual ADPLLJ
 320  */
 321 static void pll_config(u32 base, u32 n, u32 m, u32 m2,
 322                        u32 clkctrl_val, int adpllj)
 323 {
 324         const struct ad_pll *adpll = (struct ad_pll *)base;
 325         u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
 326         u32 sig_val = 0, hs_mod = 0;
 327
 328         m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
 329         mn2val = m;
 330
 331         /* calculate clkout_dco */
 332         clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
 333
 334         /* sigma delta & Hs mode selection skip for ADPLLS*/
 335         if (adpllj) {
 336                 sig_val = pll_sigma_delta_val(clkout_dco);
 337                 hs_mod = pll_dco_freq_sel(clkout_dco);
 338         }
 339
 340         /* by-pass pll */
 341         read_clkctrl = readl(&adpll->clkctrl);
 342         writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
 343         while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
 344                 != ADPLLJ_STATUS_BYPASSANDACK)
 345                 ;
 346
 347         /* clear TINITZ */
 348         read_clkctrl = readl(&adpll->clkctrl);
 349         writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
 350
 351         /*
 352          * ref_clk = 20/(n + 1);
 353          * clkout_dco = ref_clk * m;
 354          * clk_out = clkout_dco/m2;
 355         */
 356         read_clkctrl = readl(&adpll->clkctrl) &
 357                              ~(ADPLLJ_CLKCTRL_LPMODE |
 358                              ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
 359                              ADPLLJ_CLKCTRL_REGM4XEN);
 360         writel(m2nval, &adpll->m2ndiv);
 361         writel(mn2val, &adpll->mn2div);
 362
 363         /* Skip for modena(ADPLLS) */
 364         if (adpllj) {
 365                 writel(sig_val, &adpll->fracdiv);
 366                 writel((read_clkctrl | hs_mod), &adpll->clkctrl);
 367         }
 368
 369         /* Load M2, N2 dividers of ADPLL */
 370         writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
 371         writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
 372
 373         /* Load M, N dividers of ADPLL */
 374         writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
 375         writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
 376
 377         /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
 378         read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
 379         if (adpllj)
 380                 writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
 381                                                 &adpll->clkctrl);
 382
 383         /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
 384         read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
 385         writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
 386
 387         /* Wait for phase and freq lock */
 388         while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
 389                ADPLLJ_STATUS_PHSFRQLOCK)
 390                 ;
 391 }
 392
 393 static void unlock_pll_control_mmr(void)
 394 {
 395         /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
 396         writel(0x1EDA4C3D, 0x481C5040);
 397         writel(0x2FF1AC2B, 0x48140060);
 398         writel(0xF757FDC0, 0x48140064);
 399         writel(0xE2BC3A6D, 0x48140068);
 400         writel(0x1EBF131D, 0x4814006c);
 401         writel(0x6F361E05, 0x48140070);
 402 }
 403
 404 static void mpu_pll_config(void)
 405 {
 406         pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
 407 }
 408
 409 static void l3_pll_config(void)
 410 {
 411         u32 l3_osc_src, rd_osc_src = 0;
 412
 413         l3_osc_src = L3_OSC_SRC;
 414         rd_osc_src = readl(OSC_SRC_CTRL);
 415
 416         if (OSC_SRC0 == l3_osc_src)
 417                 writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
 418         else
 419                 writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
 420
 421         pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
 422 }
 423
 424 void ddr_pll_config(unsigned int ddrpll_m)
 425 {
 426         pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
 427 }
 428
 429 void sata_pll_config(void)
 430 {
 431         /*
 432          * This sequence for configuring the SATA PLL
 433          * resident in the control module is documented
 434          * in TI8148 TRM section 21.3.1
 435          */
 436         writel(SATA_PLLCFG1, &spll->pllcfg1);
 437         udelay(50);
 438
 439         writel(SATA_PLLCFG3, &spll->pllcfg3);
 440         udelay(50);
 441
 442         writel(SATA_PLLCFG0_1, &spll->pllcfg0);
 443         udelay(50);
 444
 445         writel(SATA_PLLCFG0_2, &spll->pllcfg0);
 446         udelay(50);
 447
 448         writel(SATA_PLLCFG0_3, &spll->pllcfg0);
 449         udelay(50);
 450
 451         writel(SATA_PLLCFG0_4, &spll->pllcfg0);
 452         udelay(50);
 453
 454         while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
 455                 ;
 456 }
 457
 458 void enable_emif_clocks(void) {};
 459
 460 void enable_dmm_clocks(void)
 461 {
 462         writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
 463         writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
 464         writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
 465         while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
 466                 ;
 467         writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
 468         while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
 469                 ;
 470         while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
 471                 ;
 472         writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
 473         while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
 474                 ;
 475         writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
 476         while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
 477                 ;
 478 }
 479
 480 /*
 481  * Configure the PLL/PRCM for necessary peripherals
 482  */
 483 void pll_init()
 484 {
 485         unlock_pll_control_mmr();
 486
 487         /* Enable the control module */
 488         writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
 489
 490         /* Configure PLLs */
 491         mpu_pll_config();
 492         l3_pll_config();
 493         sata_pll_config();
 494
 495         /* Enable the required peripherals */
 496         enable_per_clocks();
 497 }