2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ls102xa_soc.h>
13 unsigned int get_soc_major_rev(void)
15 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
16 unsigned int svr
, major
;
18 svr
= in_be32(&gur
->svr
);
24 int arch_soc_init(void)
26 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
27 struct ccsr_cci400
*cci
= (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR
;
30 #ifdef CONFIG_FSL_QSPI
31 out_be32(&scfg
->qspi_cfg
, SCFG_QSPI_CLKSEL
);
34 #ifdef CONFIG_FSL_DCU_FB
35 out_be32(&scfg
->pixclkcr
, SCFG_PIXCLKCR_PXCKEN
);
38 /* Configure Little endian for SAI, ASRC and SPDIF */
39 out_be32(&scfg
->endiancr
, SCFG_ENDIANCR_LE
);
42 * Enable snoop requests and DVM message requests for
43 * Slave insterface S4 (A7 core cluster)
45 out_le32(&cci
->slave
[4].snoop_ctrl
,
46 CCI400_DVM_MESSAGE_REQ_EN
| CCI400_SNOOP_REQ_EN
);
48 major
= get_soc_major_rev();
49 if (major
== SOC_MAJOR_VER_1_0
) {
51 * Set CCI-400 Slave interface S1, S2 Shareable Override
52 * Register All transactions are treated as non-shareable
54 out_le32(&cci
->slave
[1].sha_ord
, CCI400_SHAORD_NON_SHAREABLE
);
55 out_le32(&cci
->slave
[2].sha_ord
, CCI400_SHAORD_NON_SHAREABLE
);
57 /* Workaround for the issue that DDR could not respond to
58 * barrier transaction which is generated by executing DSB/ISB
59 * instruction. Set CCI-400 control override register to
60 * terminate the barrier transaction. After DDR is initialized,
61 * allow barrier transaction to DDR again */
62 out_le32(&cci
->ctrl_ord
, CCI400_CTRLORD_TERM_BARRIER
);