arch/arm/cpu/armv7/ls102xa/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <fsl_csu.h>
  15
  16 struct liodn_id_table sec_liodn_tbl[] = {
  17         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  18         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  19         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  20         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  21         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  23         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  24         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  25         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  31         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  32         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  33 };
  34
  35 struct smmu_stream_id dev_stream_id[] = {
  36         { 0x100, 0x01, "ETSEC MAC1" },
  37         { 0x104, 0x02, "ETSEC MAC2" },
  38         { 0x108, 0x03, "ETSEC MAC3" },
  39         { 0x10c, 0x04, "PEX1" },
  40         { 0x110, 0x05, "PEX2" },
  41         { 0x114, 0x06, "qDMA" },
  42         { 0x118, 0x07, "SATA" },
  43         { 0x11c, 0x08, "USB3" },
  44         { 0x120, 0x09, "QE" },
  45         { 0x124, 0x0a, "eSDHC" },
  46         { 0x128, 0x0b, "eMA" },
  47         { 0x14c, 0x0c, "2D-ACE" },
  48         { 0x150, 0x0d, "USB2" },
  49         { 0x18c, 0x0e, "DEBUG" },
  50 };
  51
  52 unsigned int get_soc_major_rev(void)
  53 {
  54         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  55         unsigned int svr, major;
  56
  57         svr = in_be32(&gur->svr);
  58         major = SVR_MAJ(svr);
  59
  60         return major;
  61 }
  62
  63 void s_init(void)
  64 {
  65 }
  66
  67 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  68 void erratum_a010315(void)
  69 {
  70         int i;
  71
  72         for (i = PCIE1; i <= PCIE2; i++)
  73                 if (!is_serdes_configured(i)) {
  74                         debug("PCIe%d: disabled all R/W permission!\n", i);
  75                         set_pcie_ns_access(i, 0);
  76                 }
  77 }
  78 #endif
  79
  80 int arch_soc_init(void)
  81 {
  82         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  83         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  84                                         CONFIG_SYS_CCI400_OFFSET);
  85         unsigned int major;
  86
  87 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  88         enable_layerscape_ns_access();
  89 #endif
  90
  91 #ifdef CONFIG_FSL_QSPI
  92         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  93 #endif
  94
  95 #ifdef CONFIG_VIDEO_FSL_DCU_FB
  96         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
  97 #endif
  98
  99         /* Configure Little endian for SAI, ASRC and SPDIF */
 100         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 101
 102         /*
 103          * Enable snoop requests and DVM message requests for
 104          * All the slave insterfaces.
 105          */
 106         out_le32(&cci->slave[0].snoop_ctrl,
 107                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 108         out_le32(&cci->slave[1].snoop_ctrl,
 109                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 110         out_le32(&cci->slave[2].snoop_ctrl,
 111                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 112         out_le32(&cci->slave[4].snoop_ctrl,
 113                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 114
 115         major = get_soc_major_rev();
 116         if (major == SOC_MAJOR_VER_1_0) {
 117                 /*
 118                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 119                  * Register All transactions are treated as non-shareable
 120                  */
 121                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 122                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 123
 124                 /* Workaround for the issue that DDR could not respond to
 125                  * barrier transaction which is generated by executing DSB/ISB
 126                  * instruction. Set CCI-400 control override register to
 127                  * terminate the barrier transaction. After DDR is initialized,
 128                  * allow barrier transaction to DDR again */
 129                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 130         }
 131
 132         /* Enable all the snoop signal for various masters */
 133         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 134                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 135                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 136                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 137                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 138                                 SCFG_SNPCNFGCR_EDMA_SNP);
 139
 140         /*
 141          * Memory controller require a register write before being enabled.
 142          * Affects: DDR
 143          * Register: EDDRTQCFG
 144          * Description: Memory controller performance is not optimal with
 145          *              default internal target queue register values.
 146          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 147          */
 148         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 149
 150         return 0;
 151 }
 152
 153 int ls102xa_smmu_stream_id_init(void)
 154 {
 155         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 156                                       ARRAY_SIZE(sec_liodn_tbl));
 157
 158         ls102xa_config_smmu_stream_id(dev_stream_id,
 159                                       ARRAY_SIZE(dev_stream_id));
 160
 161         return 0;
 162 }