arch/arm/cpu/armv7/mx5/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 #include <linux/errno.h>
  16 #include <asm/io.h>
  17 #include <asm/imx-common/boot_mode.h>
  18
  19 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  20 #error "CPU_TYPE not defined"
  21 #endif
  22
  23 u32 get_cpu_rev(void)
  24 {
  25 #ifdef CONFIG_MX51
  26         int system_rev = 0x51000;
  27 #else
  28         int system_rev = 0x53000;
  29 #endif
  30         int reg = __raw_readl(ROM_SI_REV);
  31
  32 #if defined(CONFIG_MX51)
  33         switch (reg) {
  34         case 0x02:
  35                 system_rev |= CHIP_REV_1_1;
  36                 break;
  37         case 0x10:
  38                 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  39                         system_rev |= CHIP_REV_2_5;
  40                 else
  41                         system_rev |= CHIP_REV_2_0;
  42                 break;
  43         case 0x20:
  44                 system_rev |= CHIP_REV_3_0;
  45                 break;
  46         default:
  47                 system_rev |= CHIP_REV_1_0;
  48                 break;
  49         }
  50 #else
  51         if (reg < 0x20)
  52                 system_rev |= CHIP_REV_1_0;
  53         else
  54                 system_rev |= reg;
  55 #endif
  56         return system_rev;
  57 }
  58
  59 #ifdef CONFIG_REVISION_TAG
  60 u32 __weak get_board_rev(void)
  61 {
  62         return get_cpu_rev();
  63 }
  64 #endif
  65
  66 #ifndef CONFIG_SYS_DCACHE_OFF
  67 void enable_caches(void)
  68 {
  69         /* Enable D-cache. I-cache is already enabled in start.S */
  70         dcache_enable();
  71 }
  72 #endif
  73
  74 #if defined(CONFIG_FEC_MXC)
  75 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  76 {
  77         int i;
  78         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  79         struct fuse_bank *bank = &iim->bank[1];
  80         struct fuse_bank1_regs *fuse =
  81                         (struct fuse_bank1_regs *)bank->fuse_regs;
  82
  83         for (i = 0; i < 6; i++)
  84                 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  85 }
  86 #endif
  87
  88 #ifdef CONFIG_MX53
  89 void boot_mode_apply(unsigned cfg_val)
  90 {
  91         writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
  92 }
  93 /*
  94  * cfg_val will be used for
  95  * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  96  *
  97  * If bit 28 of LPGR is set upon watchdog reset,
  98  * bits[25:0] of LPGR will move to SBMR.
  99  */
 100 const struct boot_mode soc_boot_modes[] = {
 101         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 102         /* usb or serial download */
 103         {"usb",         MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
 104         {"sata",        MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
 105         {"escpi1:0",    MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
 106         {"escpi1:1",    MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
 107         {"escpi1:2",    MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
 108         {"escpi1:3",    MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
 109         /* 4 bit bus width */
 110         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 111         {"esdhc2",      MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 112         {"esdhc3",      MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
 113         {"esdhc4",      MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
 114         {NULL,          0},
 115 };
 116 #endif