2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS
, /* System PLL */
18 PLL_BUS
, /* System Bus PLL*/
19 PLL_USBOTG
, /* OTG USB PLL */
20 PLL_ENET
, /* ENET PLL */
21 PLL_AUDIO
, /* AUDIO PLL */
22 PLL_VIDEO
, /* AUDIO PLL */
25 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable
)
32 reg
= __raw_readl(&imx_ccm
->CCGR2
);
34 reg
|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
36 reg
&= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
37 __raw_writel(reg
, &imx_ccm
->CCGR2
);
41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg
)
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm
->CCGR4
,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
55 clrsetbits_le32(&imx_ccm
->cs2cdr
,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
,
61 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
63 clrbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
65 clrsetbits_le32(&imx_ccm
->cs2cdr
,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
71 setbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
73 setbits_le32(&imx_ccm
->CCGR4
,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
82 void enable_usboh3_clk(unsigned char enable
)
86 reg
= __raw_readl(&imx_ccm
->CCGR6
);
88 reg
|= MXC_CCM_CCGR6_USBOH3_MASK
;
90 reg
&= ~(MXC_CCM_CCGR6_USBOH3_MASK
);
91 __raw_writel(reg
, &imx_ccm
->CCGR6
);
95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
96 void enable_enet_clk(unsigned char enable
)
101 mask
= MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK
;
102 addr
= &imx_ccm
->CCGR0
;
103 } else if (is_mx6ul()) {
104 mask
= MXC_CCM_CCGR3_ENET_MASK
;
105 addr
= &imx_ccm
->CCGR3
;
107 mask
= MXC_CCM_CCGR1_ENET_MASK
;
108 addr
= &imx_ccm
->CCGR1
;
112 setbits_le32(addr
, mask
);
114 clrbits_le32(addr
, mask
);
118 #ifdef CONFIG_MXC_UART
119 void enable_uart_clk(unsigned char enable
)
123 if (is_mx6ul() || is_mx6ull())
124 mask
= MXC_CCM_CCGR5_UART_MASK
;
126 mask
= MXC_CCM_CCGR5_UART_MASK
| MXC_CCM_CCGR5_UART_SERIAL_MASK
;
129 setbits_le32(&imx_ccm
->CCGR5
, mask
);
131 clrbits_le32(&imx_ccm
->CCGR5
, mask
);
136 int enable_usdhc_clk(unsigned char enable
, unsigned bus_num
)
143 mask
= MXC_CCM_CCGR_CG_MASK
<< (bus_num
* 2 + 2);
145 setbits_le32(&imx_ccm
->CCGR6
, mask
);
147 clrbits_le32(&imx_ccm
->CCGR6
, mask
);
153 #ifdef CONFIG_SYS_I2C_MXC
154 /* i2c_num can be from 0 - 3 */
155 int enable_i2c_clk(unsigned char enable
, unsigned i2c_num
)
164 mask
= MXC_CCM_CCGR_CG_MASK
165 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
167 reg
= __raw_readl(&imx_ccm
->CCGR2
);
172 __raw_writel(reg
, &imx_ccm
->CCGR2
);
174 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
175 mask
= MXC_CCM_CCGR6_I2C4_MASK
;
176 addr
= &imx_ccm
->CCGR6
;
178 mask
= MXC_CCM_CCGR1_I2C4_SERIAL_MASK
;
179 addr
= &imx_ccm
->CCGR1
;
181 reg
= __raw_readl(addr
);
186 __raw_writel(reg
, addr
);
192 /* spi_num can be from 0 - SPI_MAX_NUM */
193 int enable_spi_clk(unsigned char enable
, unsigned spi_num
)
198 if (spi_num
> SPI_MAX_NUM
)
201 mask
= MXC_CCM_CCGR_CG_MASK
<< (spi_num
<< 1);
202 reg
= __raw_readl(&imx_ccm
->CCGR1
);
207 __raw_writel(reg
, &imx_ccm
->CCGR1
);
210 static u32
decode_pll(enum pll_clocks pll
, u32 infreq
)
212 u32 div
, test_div
, pll_num
, pll_denom
;
216 div
= __raw_readl(&imx_ccm
->analog_pll_sys
);
217 div
&= BM_ANADIG_PLL_SYS_DIV_SELECT
;
219 return (infreq
* div
) >> 1;
221 div
= __raw_readl(&imx_ccm
->analog_pll_528
);
222 div
&= BM_ANADIG_PLL_528_DIV_SELECT
;
224 return infreq
* (20 + (div
<< 1));
226 div
= __raw_readl(&imx_ccm
->analog_usb1_pll_480_ctrl
);
227 div
&= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT
;
229 return infreq
* (20 + (div
<< 1));
231 div
= __raw_readl(&imx_ccm
->analog_pll_enet
);
232 div
&= BM_ANADIG_PLL_ENET_DIV_SELECT
;
234 return 25000000 * (div
+ (div
>> 1) + 1);
236 div
= __raw_readl(&imx_ccm
->analog_pll_audio
);
237 if (!(div
& BM_ANADIG_PLL_AUDIO_ENABLE
))
239 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
240 if (div
& BM_ANADIG_PLL_AUDIO_BYPASS
)
242 pll_num
= __raw_readl(&imx_ccm
->analog_pll_audio_num
);
243 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_audio_denom
);
244 test_div
= (div
& BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
) >>
245 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
;
246 div
&= BM_ANADIG_PLL_AUDIO_DIV_SELECT
;
248 debug("Error test_div\n");
251 test_div
= 1 << (2 - test_div
);
253 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
255 div
= __raw_readl(&imx_ccm
->analog_pll_video
);
256 if (!(div
& BM_ANADIG_PLL_VIDEO_ENABLE
))
258 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
259 if (div
& BM_ANADIG_PLL_VIDEO_BYPASS
)
261 pll_num
= __raw_readl(&imx_ccm
->analog_pll_video_num
);
262 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_video_denom
);
263 test_div
= (div
& BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
) >>
264 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT
;
265 div
&= BM_ANADIG_PLL_VIDEO_DIV_SELECT
;
267 debug("Error test_div\n");
270 test_div
= 1 << (2 - test_div
);
272 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
278 static u32
mxc_get_pll_pfd(enum pll_clocks pll
, int pfd_num
)
285 if (!is_mx6ul() && !is_mx6ull()) {
287 /* No PFD3 on PLL2 */
291 div
= __raw_readl(&imx_ccm
->analog_pfd_528
);
292 freq
= (u64
)decode_pll(PLL_BUS
, MXC_HCLK
);
295 div
= __raw_readl(&imx_ccm
->analog_pfd_480
);
296 freq
= (u64
)decode_pll(PLL_USBOTG
, MXC_HCLK
);
299 /* No PFD on other PLL */
303 return lldiv(freq
* 18, (div
& ANATOP_PFD_FRAC_MASK(pfd_num
)) >>
304 ANATOP_PFD_FRAC_SHIFT(pfd_num
));
307 static u32
get_mcu_main_clk(void)
311 reg
= __raw_readl(&imx_ccm
->cacrr
);
312 reg
&= MXC_CCM_CACRR_ARM_PODF_MASK
;
313 reg
>>= MXC_CCM_CACRR_ARM_PODF_OFFSET
;
314 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
316 return freq
/ (reg
+ 1);
319 u32
get_periph_clk(void)
321 u32 reg
, div
= 0, freq
= 0;
323 reg
= __raw_readl(&imx_ccm
->cbcdr
);
324 if (reg
& MXC_CCM_CBCDR_PERIPH_CLK_SEL
) {
325 div
= (reg
& MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK
) >>
326 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET
;
327 reg
= __raw_readl(&imx_ccm
->cbcmr
);
328 reg
&= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK
;
329 reg
>>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET
;
333 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
343 reg
= __raw_readl(&imx_ccm
->cbcmr
);
344 reg
&= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
;
345 reg
>>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
;
349 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
352 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
355 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
358 /* static / 2 divider */
359 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
366 return freq
/ (div
+ 1);
369 static u32
get_ipg_clk(void)
373 reg
= __raw_readl(&imx_ccm
->cbcdr
);
374 reg
&= MXC_CCM_CBCDR_IPG_PODF_MASK
;
375 ipg_podf
= reg
>> MXC_CCM_CBCDR_IPG_PODF_OFFSET
;
377 return get_ahb_clk() / (ipg_podf
+ 1);
380 static u32
get_ipg_per_clk(void)
382 u32 reg
, perclk_podf
;
384 reg
= __raw_readl(&imx_ccm
->cscmr1
);
385 if (is_mx6sl() || is_mx6sx() ||
386 is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
387 if (reg
& MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
)
388 return MXC_HCLK
; /* OSC 24Mhz */
391 perclk_podf
= reg
& MXC_CCM_CSCMR1_PERCLK_PODF_MASK
;
393 return get_ipg_clk() / (perclk_podf
+ 1);
396 static u32
get_uart_clk(void)
399 u32 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
) / 6; /* static divider */
400 reg
= __raw_readl(&imx_ccm
->cscdr1
);
402 if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
404 if (reg
& MXC_CCM_CSCDR1_UART_CLK_SEL
)
408 reg
&= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
;
409 uart_podf
= reg
>> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
;
411 return freq
/ (uart_podf
+ 1);
414 static u32
get_cspi_clk(void)
418 reg
= __raw_readl(&imx_ccm
->cscdr2
);
419 cspi_podf
= (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK
) >>
420 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET
;
422 if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
424 if (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK
)
425 return MXC_HCLK
/ (cspi_podf
+ 1);
428 return decode_pll(PLL_USBOTG
, MXC_HCLK
) / (8 * (cspi_podf
+ 1));
431 static u32
get_axi_clk(void)
433 u32 root_freq
, axi_podf
;
434 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
436 axi_podf
= cbcdr
& MXC_CCM_CBCDR_AXI_PODF_MASK
;
437 axi_podf
>>= MXC_CCM_CBCDR_AXI_PODF_OFFSET
;
439 if (cbcdr
& MXC_CCM_CBCDR_AXI_SEL
) {
440 if (cbcdr
& MXC_CCM_CBCDR_AXI_ALT_SEL
)
441 root_freq
= mxc_get_pll_pfd(PLL_USBOTG
, 1);
443 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
445 root_freq
= get_periph_clk();
447 return root_freq
/ (axi_podf
+ 1);
450 static u32
get_emi_slow_clk(void)
452 u32 emi_clk_sel
, emi_slow_podf
, cscmr1
, root_freq
= 0;
454 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
455 emi_clk_sel
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK
;
456 emi_clk_sel
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET
;
457 emi_slow_podf
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK
;
458 emi_slow_podf
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET
;
460 switch (emi_clk_sel
) {
462 root_freq
= get_axi_clk();
465 root_freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
468 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
471 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
475 return root_freq
/ (emi_slow_podf
+ 1);
478 static u32
get_mmdc_ch0_clk(void)
480 u32 cbcmr
= __raw_readl(&imx_ccm
->cbcmr
);
481 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
483 u32 freq
, podf
, per2_clk2_podf
, pmu_misc2_audio_div
;
485 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
486 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK
) >>
487 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET
;
488 if (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK_SEL
) {
489 per2_clk2_podf
= (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK
) >>
490 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET
;
492 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
495 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
497 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
498 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
500 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
505 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
) >>
506 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
) {
508 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
511 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
514 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
518 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) >> 1;
522 pmu_misc2_audio_div
= PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm
->pmu_misc2
));
523 switch (pmu_misc2_audio_div
) {
526 pmu_misc2_audio_div
= 1;
529 pmu_misc2_audio_div
= 2;
532 pmu_misc2_audio_div
= 4;
535 freq
= decode_pll(PLL_AUDIO
, MXC_HCLK
) /
540 return freq
/ (podf
+ 1) / (per2_clk2_podf
+ 1);
542 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK
) >>
543 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET
;
544 return get_periph_clk() / (podf
+ 1);
548 #if defined(CONFIG_VIDEO_MXS)
549 static int enable_pll_video(u32 pll_div
, u32 pll_num
, u32 pll_denom
,
555 debug("pll5 div = %d, num = %d, denom = %d\n",
556 pll_div
, pll_num
, pll_denom
);
558 /* Power up PLL5 video */
559 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN
|
560 BM_ANADIG_PLL_VIDEO_BYPASS
|
561 BM_ANADIG_PLL_VIDEO_DIV_SELECT
|
562 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
,
563 &imx_ccm
->analog_pll_video_clr
);
565 /* Set div, num and denom */
568 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
569 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
570 &imx_ccm
->analog_pll_video_set
);
573 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
574 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
575 &imx_ccm
->analog_pll_video_set
);
578 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
579 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
580 &imx_ccm
->analog_pll_video_set
);
583 puts("Wrong test_div!\n");
587 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num
),
588 &imx_ccm
->analog_pll_video_num
);
589 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom
),
590 &imx_ccm
->analog_pll_video_denom
);
593 start
= get_timer(0); /* Get current timestamp */
596 reg
= readl(&imx_ccm
->analog_pll_video
);
597 if (reg
& BM_ANADIG_PLL_VIDEO_LOCK
) {
599 writel(BM_ANADIG_PLL_VIDEO_ENABLE
,
600 &imx_ccm
->analog_pll_video_set
);
603 } while (get_timer(0) < (start
+ 10)); /* Wait 10ms */
605 puts("Lock PLL5 timeout\n");
611 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
613 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
615 void mxs_set_lcdclk(u32 base_addr
, u32 freq
)
618 u32 hck
= MXC_HCLK
/ 1000;
619 /* DIV_SELECT ranges from 27 to 54 */
623 u32 i
, j
, max_pred
= 8, max_postd
= 8, pred
= 1, postd
= 1;
624 u32 pll_div
, pll_num
, pll_denom
, post_div
= 1;
626 debug("mxs_set_lcdclk, freq = %dKHz\n", freq
);
628 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
629 debug("This chip not support lcd!\n");
633 if (base_addr
== LCDIF1_BASE_ADDR
) {
634 reg
= readl(&imx_ccm
->cscdr2
);
635 /* Can't change clocks when clock not from pre-mux */
636 if ((reg
& MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
) != 0)
641 reg
= readl(&imx_ccm
->cscdr2
);
642 /* Can't change clocks when clock not from pre-mux */
643 if ((reg
& MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
) != 0)
647 temp
= freq
* max_pred
* max_postd
;
650 * Register: PLL_VIDEO
651 * Bit Field: POST_DIV_SELECT
652 * 00 — Divide by 4.
653 * 01 — Divide by 2.
654 * 10 — Divide by 1.
656 * No need to check post_div(1)
658 for (post_div
= 2; post_div
<= 4; post_div
<<= 1) {
659 if ((temp
* post_div
) > min
) {
666 printf("Fail to set rate to %dkhz", freq
);
671 /* Choose the best pred and postd to match freq for lcd */
672 for (i
= 1; i
<= max_pred
; i
++) {
673 for (j
= 1; j
<= max_postd
; j
++) {
675 if (temp
> max
|| temp
< min
)
677 if (best
== 0 || temp
< best
) {
686 printf("Fail to set rate to %dKHz", freq
);
690 debug("best %d, pred = %d, postd = %d\n", best
, pred
, postd
);
692 pll_div
= best
/ hck
;
694 pll_num
= (best
- hck
* pll_div
) * pll_denom
/ hck
;
698 * (24MHz * (pll_div + --------- ))
700 *freq KHz = --------------------------------
701 * post_div * pred * postd * 1000
704 if (base_addr
== LCDIF1_BASE_ADDR
) {
705 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
708 /* Select pre-lcd clock to PLL5 and set pre divider */
709 clrsetbits_le32(&imx_ccm
->cscdr2
,
710 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK
|
711 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK
,
712 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET
) |
714 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET
));
716 /* Set the post divider */
717 clrsetbits_le32(&imx_ccm
->cbcmr
,
718 MXC_CCM_CBCMR_LCDIF1_PODF_MASK
,
720 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET
));
721 } else if (is_mx6sx()) {
722 /* Setting LCDIF2 for i.MX6SX */
723 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
726 /* Select pre-lcd clock to PLL5 and set pre divider */
727 clrsetbits_le32(&imx_ccm
->cscdr2
,
728 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK
|
729 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK
,
730 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET
) |
732 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET
));
734 /* Set the post divider */
735 clrsetbits_le32(&imx_ccm
->cscmr1
,
736 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK
,
738 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET
));
742 int enable_lcdif_clock(u32 base_addr
)
745 u32 lcdif_clk_sel_mask
, lcdif_ccgr3_mask
;
748 if ((base_addr
!= LCDIF1_BASE_ADDR
) &&
749 (base_addr
!= LCDIF2_BASE_ADDR
)) {
750 puts("Wrong LCD interface!\n");
753 /* Set to pre-mux clock at default */
754 lcdif_clk_sel_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
755 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
:
756 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
757 lcdif_ccgr3_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
758 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK
|
759 MXC_CCM_CCGR3_DISP_AXI_MASK
) :
760 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK
|
761 MXC_CCM_CCGR3_DISP_AXI_MASK
);
762 } else if (is_mx6ul() || is_mx6ull()) {
763 if (base_addr
!= LCDIF1_BASE_ADDR
) {
764 puts("Wrong LCD interface!\n");
767 /* Set to pre-mux clock at default */
768 lcdif_clk_sel_mask
= MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
769 lcdif_ccgr3_mask
= MXC_CCM_CCGR3_LCDIF1_PIX_MASK
;
774 reg
= readl(&imx_ccm
->cscdr2
);
775 reg
&= ~lcdif_clk_sel_mask
;
776 writel(reg
, &imx_ccm
->cscdr2
);
778 /* Enable the LCDIF pix clock */
779 reg
= readl(&imx_ccm
->CCGR3
);
780 reg
|= lcdif_ccgr3_mask
;
781 writel(reg
, &imx_ccm
->CCGR3
);
783 reg
= readl(&imx_ccm
->CCGR2
);
784 reg
|= MXC_CCM_CCGR2_LCD_MASK
;
785 writel(reg
, &imx_ccm
->CCGR2
);
791 #ifdef CONFIG_FSL_QSPI
792 /* qspi_num can be from 0 - 1 */
793 void enable_qspi_clk(int qspi_num
)
796 /* Enable QuadSPI clock */
799 /* disable the clock gate */
800 clrbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
802 /* set 50M : (50 = 396 / 2 / 4) */
803 reg
= readl(&imx_ccm
->cscmr1
);
804 reg
&= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK
|
805 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK
);
806 reg
|= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET
) |
807 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET
));
808 writel(reg
, &imx_ccm
->cscmr1
);
810 /* enable the clock gate */
811 setbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
815 * disable the clock gate
816 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
817 * disable both of them.
819 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
820 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
822 /* set 50M : (50 = 396 / 2 / 4) */
823 reg
= readl(&imx_ccm
->cs2cdr
);
824 reg
&= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
825 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
826 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
);
827 reg
|= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
828 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
829 writel(reg
, &imx_ccm
->cs2cdr
);
831 /*enable the clock gate*/
832 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
833 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
841 #ifdef CONFIG_FEC_MXC
842 int enable_fec_anatop_clock(int fec_id
, enum enet_freq freq
)
845 s32 timeout
= 100000;
847 struct anatop_regs __iomem
*anatop
=
848 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
850 if (freq
< ENET_25MHZ
|| freq
> ENET_125MHZ
)
853 reg
= readl(&anatop
->pll_enet
);
856 reg
&= ~BM_ANADIG_PLL_ENET_DIV_SELECT
;
857 reg
|= BF_ANADIG_PLL_ENET_DIV_SELECT(freq
);
858 } else if (fec_id
== 1) {
859 /* Only i.MX6SX/UL support ENET2 */
860 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
862 reg
&= ~BM_ANADIG_PLL_ENET2_DIV_SELECT
;
863 reg
|= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq
);
868 if ((reg
& BM_ANADIG_PLL_ENET_POWERDOWN
) ||
869 (!(reg
& BM_ANADIG_PLL_ENET_LOCK
))) {
870 reg
&= ~BM_ANADIG_PLL_ENET_POWERDOWN
;
871 writel(reg
, &anatop
->pll_enet
);
873 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_ENET_LOCK
)
880 /* Enable FEC clock */
882 reg
|= BM_ANADIG_PLL_ENET_ENABLE
;
884 reg
|= BM_ANADIG_PLL_ENET2_ENABLE
;
885 reg
&= ~BM_ANADIG_PLL_ENET_BYPASS
;
886 writel(reg
, &anatop
->pll_enet
);
889 /* Disable enet system clcok before switching clock parent */
890 reg
= readl(&imx_ccm
->CCGR3
);
891 reg
&= ~MXC_CCM_CCGR3_ENET_MASK
;
892 writel(reg
, &imx_ccm
->CCGR3
);
895 * Set enet ahb clock to 200MHz
896 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
898 reg
= readl(&imx_ccm
->chsccdr
);
899 reg
&= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
900 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
901 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK
);
903 reg
|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET
);
905 reg
|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET
);
906 reg
|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET
);
907 writel(reg
, &imx_ccm
->chsccdr
);
909 /* Enable enet system clock */
910 reg
= readl(&imx_ccm
->CCGR3
);
911 reg
|= MXC_CCM_CCGR3_ENET_MASK
;
912 writel(reg
, &imx_ccm
->CCGR3
);
918 static u32
get_usdhc_clk(u32 port
)
920 u32 root_freq
= 0, usdhc_podf
= 0, clk_sel
= 0;
921 u32 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
922 u32 cscdr1
= __raw_readl(&imx_ccm
->cscdr1
);
926 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC1_PODF_MASK
) >>
927 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET
;
928 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC1_CLK_SEL
;
932 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC2_PODF_MASK
) >>
933 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET
;
934 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC2_CLK_SEL
;
938 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC3_PODF_MASK
) >>
939 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET
;
940 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC3_CLK_SEL
;
944 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC4_PODF_MASK
) >>
945 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET
;
946 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC4_CLK_SEL
;
954 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
956 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
958 return root_freq
/ (usdhc_podf
+ 1);
961 u32
imx_get_uartclk(void)
963 return get_uart_clk();
966 u32
imx_get_fecclk(void)
968 return mxc_get_clock(MXC_IPG_CLK
);
971 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
972 static int enable_enet_pll(uint32_t en
)
974 struct mxc_ccm_reg
*const imx_ccm
975 = (struct mxc_ccm_reg
*) CCM_BASE_ADDR
;
976 s32 timeout
= 100000;
980 reg
= readl(&imx_ccm
->analog_pll_enet
);
981 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
982 writel(reg
, &imx_ccm
->analog_pll_enet
);
983 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
985 if (readl(&imx_ccm
->analog_pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
990 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
991 writel(reg
, &imx_ccm
->analog_pll_enet
);
993 writel(reg
, &imx_ccm
->analog_pll_enet
);
998 #ifdef CONFIG_CMD_SATA
999 static void ungate_sata_clock(void)
1001 struct mxc_ccm_reg
*const imx_ccm
=
1002 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1004 /* Enable SATA clock. */
1005 setbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1008 int enable_sata_clock(void)
1010 ungate_sata_clock();
1011 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
);
1014 void disable_sata_clock(void)
1016 struct mxc_ccm_reg
*const imx_ccm
=
1017 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1019 clrbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1023 #ifdef CONFIG_PCIE_IMX
1024 static void ungate_pcie_clock(void)
1026 struct mxc_ccm_reg
*const imx_ccm
=
1027 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1029 /* Enable PCIe clock. */
1030 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_PCIE_MASK
);
1033 int enable_pcie_clock(void)
1035 struct anatop_regs
*anatop_regs
=
1036 (struct anatop_regs
*)ANATOP_BASE_ADDR
;
1037 struct mxc_ccm_reg
*ccm_regs
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1043 * The register ANATOP_MISC1 is not documented in the Freescale
1044 * MX6RM. The register that is mapped in the ANATOP space and
1045 * marked as ANATOP_MISC1 is actually documented in the PMU section
1046 * of the datasheet as PMU_MISC1.
1048 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1049 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1050 * for PCI express link that is clocked from the i.MX6.
1052 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1053 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1054 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1055 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1056 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1059 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF
;
1061 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF
;
1063 clrsetbits_le32(&anatop_regs
->ana_misc1
,
1064 ANADIG_ANA_MISC1_LVDSCLK1_IBEN
|
1065 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK
,
1066 ANADIG_ANA_MISC1_LVDSCLK1_OBEN
| lvds1_clk_sel
);
1068 /* PCIe reference clock sourced from AXI. */
1069 clrbits_le32(&ccm_regs
->cbcmr
, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL
);
1071 /* Party time! Ungate the clock to the PCIe. */
1072 #ifdef CONFIG_CMD_SATA
1073 ungate_sata_clock();
1075 ungate_pcie_clock();
1077 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
|
1078 BM_ANADIG_PLL_ENET_ENABLE_PCIE
);
1082 #ifdef CONFIG_SECURE_BOOT
1083 void hab_caam_clock_enable(unsigned char enable
)
1088 /* CG5, DCP clock */
1089 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1091 reg
|= MXC_CCM_CCGR0_DCP_CLK_MASK
;
1093 reg
&= ~MXC_CCM_CCGR0_DCP_CLK_MASK
;
1094 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1096 /* CG4 ~ CG6, CAAM clocks */
1097 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1099 reg
|= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1100 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1101 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1103 reg
&= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1104 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1105 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1106 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1110 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1112 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1114 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1115 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1119 static void enable_pll3(void)
1121 struct anatop_regs __iomem
*anatop
=
1122 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
1124 /* make sure pll3 is enabled */
1125 if ((readl(&anatop
->usb1_pll_480_ctrl
) &
1126 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0) {
1127 /* enable pll's power */
1128 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER
,
1129 &anatop
->usb1_pll_480_ctrl_set
);
1130 writel(0x80, &anatop
->ana_misc2_clr
);
1131 /* wait for pll lock */
1132 while ((readl(&anatop
->usb1_pll_480_ctrl
) &
1133 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0)
1135 /* disable bypass */
1136 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS
,
1137 &anatop
->usb1_pll_480_ctrl_clr
);
1138 /* enable pll output */
1139 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE
,
1140 &anatop
->usb1_pll_480_ctrl_set
);
1144 void enable_thermal_clk(void)
1149 unsigned int mxc_get_clock(enum mxc_clock clk
)
1153 return get_mcu_main_clk();
1155 return get_periph_clk();
1157 return get_ahb_clk();
1159 return get_ipg_clk();
1160 case MXC_IPG_PERCLK
:
1162 return get_ipg_per_clk();
1164 return get_uart_clk();
1166 return get_cspi_clk();
1168 return get_axi_clk();
1169 case MXC_EMI_SLOW_CLK
:
1170 return get_emi_slow_clk();
1172 return get_mmdc_ch0_clk();
1174 return get_usdhc_clk(0);
1175 case MXC_ESDHC2_CLK
:
1176 return get_usdhc_clk(1);
1177 case MXC_ESDHC3_CLK
:
1178 return get_usdhc_clk(2);
1179 case MXC_ESDHC4_CLK
:
1180 return get_usdhc_clk(3);
1182 return get_ahb_clk();
1184 printf("Unsupported MXC CLK: %d\n", clk
);
1192 * Dump some core clockes.
1194 int do_mx6_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
1197 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
1198 printf("PLL_SYS %8d MHz\n", freq
/ 1000000);
1199 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
1200 printf("PLL_BUS %8d MHz\n", freq
/ 1000000);
1201 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
1202 printf("PLL_OTG %8d MHz\n", freq
/ 1000000);
1203 freq
= decode_pll(PLL_ENET
, MXC_HCLK
);
1204 printf("PLL_NET %8d MHz\n", freq
/ 1000000);
1207 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK
) / 1000);
1208 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK
) / 1000);
1209 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK
) / 1000);
1210 #ifdef CONFIG_MXC_SPI
1211 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK
) / 1000);
1213 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000);
1214 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK
) / 1000);
1215 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK
) / 1000);
1216 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK
) / 1000);
1217 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK
) / 1000);
1218 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK
) / 1000);
1219 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK
) / 1000);
1220 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK
) / 1000);
1221 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK
) / 1000);
1226 #ifndef CONFIG_MX6SX
1227 void enable_ipu_clock(void)
1229 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1231 reg
= readl(&mxc_ccm
->CCGR3
);
1232 reg
|= MXC_CCM_CCGR3_IPU1_IPU_MASK
;
1233 writel(reg
, &mxc_ccm
->CCGR3
);
1236 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_PRG_CLK0_MASK
);
1237 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_IPU2_IPU_MASK
);
1242 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1243 defined(CONFIG_MX6S)
1244 static void disable_ldb_di_clock_sources(void)
1246 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1249 /* Make sure PFDs are disabled at boot. */
1250 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1251 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1256 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1258 /* Disable PLL3 PFDs */
1259 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1261 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1264 reg
= readl(&mxc_ccm
->analog_pll_video
);
1266 writel(reg
, &mxc_ccm
->analog_pll_video
);
1269 static void enable_ldb_di_clock_sources(void)
1271 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1274 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1276 reg
&= ~(0x80008080);
1278 reg
&= ~(0x80808080);
1279 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1281 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1282 reg
&= ~(0x80808080);
1283 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1287 * Try call this function as early in the boot process as possible since the
1288 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1290 void select_ldb_di_clock_source(enum ldb_di_clock clk
)
1292 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1296 * Need to follow a strict procedure when changing the LDB
1297 * clock, else we can introduce a glitch. Things to keep in
1299 * 1. The current and new parent clocks must be disabled.
1300 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1302 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1303 * the top four options are in one mux and the PLL3 option along
1304 * with another option is in the second mux. There is third mux
1305 * used to decide between the first and second mux.
1306 * The code below switches the parent to the bottom mux first
1307 * and then manipulates the top mux. This ensures that no glitch
1308 * will enter the divider.
1310 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1311 * for this clock. The only way to disable this clock is to move
1312 * it to pll3_sw_clk and then to disable pll3_sw_clk
1313 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1316 /* Disable all ldb_di clock parents */
1317 disable_ldb_di_clock_sources();
1319 /* Set MMDC_CH1 mask bit */
1320 reg
= readl(&mxc_ccm
->ccdr
);
1321 reg
|= MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1322 writel(reg
, &mxc_ccm
->ccdr
);
1324 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1325 reg
= readl(&mxc_ccm
->cbcmr
);
1326 reg
&= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
;
1327 writel(reg
, &mxc_ccm
->cbcmr
);
1330 * Set the periph2_clk_sel to the top mux so that
1331 * mmdc_ch1 is from pll3_sw_clk.
1333 reg
= readl(&mxc_ccm
->cbcdr
);
1334 reg
|= MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1335 writel(reg
, &mxc_ccm
->cbcdr
);
1337 /* Wait for the clock switch */
1338 while (readl(&mxc_ccm
->cdhipr
))
1340 /* Disable pll3_sw_clk by selecting bypass clock source */
1341 reg
= readl(&mxc_ccm
->ccsr
);
1342 reg
|= MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1343 writel(reg
, &mxc_ccm
->ccsr
);
1345 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1346 reg
= readl(&mxc_ccm
->cs2cdr
);
1347 reg
|= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1348 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1349 writel(reg
, &mxc_ccm
->cs2cdr
);
1351 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1352 reg
= readl(&mxc_ccm
->cs2cdr
);
1353 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1354 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1355 reg
|= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1356 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1357 writel(reg
, &mxc_ccm
->cs2cdr
);
1359 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1360 reg
= readl(&mxc_ccm
->cs2cdr
);
1361 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1362 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1363 reg
|= ((clk
<< MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1364 | (clk
<< MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1365 writel(reg
, &mxc_ccm
->cs2cdr
);
1367 /* Unbypass pll3_sw_clk */
1368 reg
= readl(&mxc_ccm
->ccsr
);
1369 reg
&= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1370 writel(reg
, &mxc_ccm
->ccsr
);
1373 * Set the periph2_clk_sel back to the bottom mux so that
1374 * mmdc_ch1 is from its original parent.
1376 reg
= readl(&mxc_ccm
->cbcdr
);
1377 reg
&= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1378 writel(reg
, &mxc_ccm
->cbcdr
);
1380 /* Wait for the clock switch */
1381 while (readl(&mxc_ccm
->cdhipr
))
1383 /* Clear MMDC_CH1 mask bit */
1384 reg
= readl(&mxc_ccm
->ccdr
);
1385 reg
&= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1386 writel(reg
, &mxc_ccm
->ccdr
);
1388 enable_ldb_di_clock_sources();
1392 #ifndef CONFIG_SYS_NO_FLASH
1393 void enable_eim_clk(unsigned char enable
)
1397 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1399 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1401 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1402 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1406 /***************************************************/
1409 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx6_showclocks
,