arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/errno.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/imx-common/boot_mode.h>
  33 #include <stdbool.h>
  34
  35 struct scu_regs {
  36         u32     ctrl;
  37         u32     config;
  38         u32     status;
  39         u32     invalidate;
  40         u32     fpga_rev;
  41 };
  42
  43 u32 get_cpu_rev(void)
  44 {
  45         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  46         u32 reg = readl(&anatop->digprog_sololite);
  47         u32 type = ((reg >> 16) & 0xff);
  48
  49         if (type != MXC_CPU_MX6SL) {
  50                 reg = readl(&anatop->digprog);
  51                 type = ((reg >> 16) & 0xff);
  52                 if (type == MXC_CPU_MX6DL) {
  53                         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  54                         u32 cfg = readl(&scu->config) & 3;
  55
  56                         if (!cfg)
  57                                 type = MXC_CPU_MX6SOLO;
  58                 }
  59         }
  60         reg &= 0xff;            /* mx6 silicon revision */
  61         return (type << 12) | (reg + 0x10);
  62 }
  63
  64 void init_aips(void)
  65 {
  66         struct aipstz_regs *aips1, *aips2;
  67
  68         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  69         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  70
  71         /*
  72          * Set all MPROTx to be non-bufferable, trusted for R/W,
  73          * not forced to user-mode.
  74          */
  75         writel(0x77777777, &aips1->mprot0);
  76         writel(0x77777777, &aips1->mprot1);
  77         writel(0x77777777, &aips2->mprot0);
  78         writel(0x77777777, &aips2->mprot1);
  79
  80         /*
  81          * Set all OPACRx to be non-bufferable, not require
  82          * supervisor privilege level for access,allow for
  83          * write access and untrusted master access.
  84          */
  85         writel(0x00000000, &aips1->opacr0);
  86         writel(0x00000000, &aips1->opacr1);
  87         writel(0x00000000, &aips1->opacr2);
  88         writel(0x00000000, &aips1->opacr3);
  89         writel(0x00000000, &aips1->opacr4);
  90         writel(0x00000000, &aips2->opacr0);
  91         writel(0x00000000, &aips2->opacr1);
  92         writel(0x00000000, &aips2->opacr2);
  93         writel(0x00000000, &aips2->opacr3);
  94         writel(0x00000000, &aips2->opacr4);
  95 }
  96
  97 /*
  98  * Set the VDDSOC
  99  *
 100  * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 101  * them to the specified millivolt level.
 102  * Possible values are from 0.725V to 1.450V in steps of
 103  * 0.025V (25mV).
 104  */
 105 void set_vddsoc(u32 mv)
 106 {
 107         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 108         u32 val, reg = readl(&anatop->reg_core);
 109
 110         if (mv < 725)
 111                 val = 0x00;     /* Power gated off */
 112         else if (mv > 1450)
 113                 val = 0x1F;     /* Power FET switched full on. No regulation */
 114         else
 115                 val = (mv - 700) / 25;
 116
 117         /*
 118          * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 119          * and set them to the calculated value (0.7V + val * 0.25V)
 120          */
 121         reg = (reg & ~(0x1F << 18)) | (val << 18);
 122         writel(reg, &anatop->reg_core);
 123 }
 124
 125 static void imx_set_wdog_powerdown(bool enable)
 126 {
 127         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 128         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 129
 130         /* Write to the PDE (Power Down Enable) bit */
 131         writew(enable, &wdog1->wmcr);
 132         writew(enable, &wdog2->wmcr);
 133 }
 134
 135 int arch_cpu_init(void)
 136 {
 137         init_aips();
 138
 139         set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
 140
 141         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 142         return 0;
 143 }
 144
 145 #ifndef CONFIG_SYS_DCACHE_OFF
 146 void enable_caches(void)
 147 {
 148         /* Enable D-cache. I-cache is already enabled in start.S */
 149         dcache_enable();
 150 }
 151 #endif
 152
 153 #if defined(CONFIG_FEC_MXC)
 154 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 155 {
 156         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 157         struct fuse_bank *bank = &iim->bank[4];
 158         struct fuse_bank4_regs *fuse =
 159                         (struct fuse_bank4_regs *)bank->fuse_regs;
 160
 161         u32 value = readl(&fuse->mac_addr_high);
 162         mac[0] = (value >> 8);
 163         mac[1] = value ;
 164
 165         value = readl(&fuse->mac_addr_low);
 166         mac[2] = value >> 24 ;
 167         mac[3] = value >> 16 ;
 168         mac[4] = value >> 8 ;
 169         mac[5] = value ;
 170
 171 }
 172 #endif
 173
 174 void boot_mode_apply(unsigned cfg_val)
 175 {
 176         unsigned reg;
 177         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 178         writel(cfg_val, &psrc->gpr9);
 179         reg = readl(&psrc->gpr10);
 180         if (cfg_val)
 181                 reg |= 1 << 28;
 182         else
 183                 reg &= ~(1 << 28);
 184         writel(reg, &psrc->gpr10);
 185 }
 186 /*
 187  * cfg_val will be used for
 188  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 189  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 190  * to SBMR1, which will determine the boot device.
 191  */
 192 const struct boot_mode soc_boot_modes[] = {
 193         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 194         /* reserved value should start rom usb */
 195         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 196         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 197         {"escpi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 198         {"escpi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 199         {"escpi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 200         {"escpi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 201         /* 4 bit bus width */
 202         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 203         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 204         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 205         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 206         {NULL,          0},
 207 };
 208
 209 void s_init(void)
 210 {
 211 }