arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/dma.h>
  18 #include <asm/imx-common/hab.h>
  19 #include <stdbool.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <dm.h>
  23 #include <imx_thermal.h>
  24 #include <mmc.h>
  25
  26 enum ldo_reg {
  27         LDO_ARM,
  28         LDO_SOC,
  29         LDO_PU,
  30 };
  31
  32 struct scu_regs {
  33         u32     ctrl;
  34         u32     config;
  35         u32     status;
  36         u32     invalidate;
  37         u32     fpga_rev;
  38 };
  39
  40 #if defined(CONFIG_IMX_THERMAL)
  41 static const struct imx_thermal_plat imx6_thermal_plat = {
  42         .regs = (void *)ANATOP_BASE_ADDR,
  43         .fuse_bank = 1,
  44         .fuse_word = 6,
  45 };
  46
  47 U_BOOT_DEVICE(imx6_thermal) = {
  48         .name = "imx_thermal",
  49         .platdata = &imx6_thermal_plat,
  50 };
  51 #endif
  52
  53 #if defined(CONFIG_SECURE_BOOT)
  54 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  55         .bank = 0,
  56         .word = 6,
  57 };
  58 #endif
  59
  60 u32 get_nr_cpus(void)
  61 {
  62         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  63         return readl(&scu->config) & 3;
  64 }
  65
  66 u32 get_cpu_rev(void)
  67 {
  68         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  69         u32 reg = readl(&anatop->digprog_sololite);
  70         u32 type = ((reg >> 16) & 0xff);
  71         u32 major, cfg = 0;
  72
  73         if (type != MXC_CPU_MX6SL) {
  74                 reg = readl(&anatop->digprog);
  75                 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  76                 cfg = readl(&scu->config) & 3;
  77                 type = ((reg >> 16) & 0xff);
  78                 if (type == MXC_CPU_MX6DL) {
  79                         if (!cfg)
  80                                 type = MXC_CPU_MX6SOLO;
  81                 }
  82
  83                 if (type == MXC_CPU_MX6Q) {
  84                         if (cfg == 1)
  85                                 type = MXC_CPU_MX6D;
  86                 }
  87
  88         }
  89         major = ((reg >> 8) & 0xff);
  90         if ((major >= 1) &&
  91             ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  92                 major--;
  93                 type = MXC_CPU_MX6QP;
  94                 if (cfg == 1)
  95                         type = MXC_CPU_MX6DP;
  96         }
  97         reg &= 0xff;            /* mx6 silicon revision */
  98         return (type << 12) | (reg + (0x10 * (major + 1)));
  99 }
 100
 101 /*
 102  * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
 103  * defines a 2-bit SPEED_GRADING
 104  */
 105 #define OCOTP_CFG3_SPEED_SHIFT  16
 106 #define OCOTP_CFG3_SPEED_800MHZ 0
 107 #define OCOTP_CFG3_SPEED_850MHZ 1
 108 #define OCOTP_CFG3_SPEED_1GHZ   2
 109 #define OCOTP_CFG3_SPEED_1P2GHZ 3
 110
 111 u32 get_cpu_speed_grade_hz(void)
 112 {
 113         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 114         struct fuse_bank *bank = &ocotp->bank[0];
 115         struct fuse_bank0_regs *fuse =
 116                 (struct fuse_bank0_regs *)bank->fuse_regs;
 117         uint32_t val;
 118
 119         val = readl(&fuse->cfg3);
 120         val >>= OCOTP_CFG3_SPEED_SHIFT;
 121         val &= 0x3;
 122
 123         switch (val) {
 124         /* Valid for IMX6DQ */
 125         case OCOTP_CFG3_SPEED_1P2GHZ:
 126                 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 127                         return 1200000000;
 128         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 129         case OCOTP_CFG3_SPEED_1GHZ:
 130                 return 996000000;
 131         /* Valid for IMX6DQ */
 132         case OCOTP_CFG3_SPEED_850MHZ:
 133                 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 134                         return 852000000;
 135         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 136         case OCOTP_CFG3_SPEED_800MHZ:
 137                 return 792000000;
 138         }
 139         return 0;
 140 }
 141
 142 /*
 143  * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
 144  * defines a 2-bit Temperature Grade
 145  *
 146  * return temperature grade and min/max temperature in celcius
 147  */
 148 #define OCOTP_MEM0_TEMP_SHIFT          6
 149
 150 u32 get_cpu_temp_grade(int *minc, int *maxc)
 151 {
 152         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 153         struct fuse_bank *bank = &ocotp->bank[1];
 154         struct fuse_bank1_regs *fuse =
 155                 (struct fuse_bank1_regs *)bank->fuse_regs;
 156         uint32_t val;
 157
 158         val = readl(&fuse->mem0);
 159         val >>= OCOTP_MEM0_TEMP_SHIFT;
 160         val &= 0x3;
 161
 162         if (minc && maxc) {
 163                 if (val == TEMP_AUTOMOTIVE) {
 164                         *minc = -40;
 165                         *maxc = 125;
 166                 } else if (val == TEMP_INDUSTRIAL) {
 167                         *minc = -40;
 168                         *maxc = 105;
 169                 } else if (val == TEMP_EXTCOMMERCIAL) {
 170                         *minc = -20;
 171                         *maxc = 105;
 172                 } else {
 173                         *minc = 0;
 174                         *maxc = 95;
 175                 }
 176         }
 177         return val;
 178 }
 179
 180 #ifdef CONFIG_REVISION_TAG
 181 u32 __weak get_board_rev(void)
 182 {
 183         u32 cpurev = get_cpu_rev();
 184         u32 type = ((cpurev >> 12) & 0xff);
 185         if (type == MXC_CPU_MX6SOLO)
 186                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 187
 188         if (type == MXC_CPU_MX6D)
 189                 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
 190
 191         return cpurev;
 192 }
 193 #endif
 194
 195 static void clear_ldo_ramp(void)
 196 {
 197         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 198         int reg;
 199
 200         /* ROM may modify LDO ramp up time according to fuse setting, so in
 201          * order to be in the safe side we neeed to reset these settings to
 202          * match the reset value: 0'b00
 203          */
 204         reg = readl(&anatop->ana_misc2);
 205         reg &= ~(0x3f << 24);
 206         writel(reg, &anatop->ana_misc2);
 207 }
 208
 209 /*
 210  * Set the PMU_REG_CORE register
 211  *
 212  * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 213  * Possible values are from 0.725V to 1.450V in steps of
 214  * 0.025V (25mV).
 215  */
 216 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 217 {
 218         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 219         u32 val, step, old, reg = readl(&anatop->reg_core);
 220         u8 shift;
 221
 222         if (mv < 725)
 223                 val = 0x00;     /* Power gated off */
 224         else if (mv > 1450)
 225                 val = 0x1F;     /* Power FET switched full on. No regulation */
 226         else
 227                 val = (mv - 700) / 25;
 228
 229         clear_ldo_ramp();
 230
 231         switch (ldo) {
 232         case LDO_SOC:
 233                 shift = 18;
 234                 break;
 235         case LDO_PU:
 236                 shift = 9;
 237                 break;
 238         case LDO_ARM:
 239                 shift = 0;
 240                 break;
 241         default:
 242                 return -EINVAL;
 243         }
 244
 245         old = (reg & (0x1F << shift)) >> shift;
 246         step = abs(val - old);
 247         if (step == 0)
 248                 return 0;
 249
 250         reg = (reg & ~(0x1F << shift)) | (val << shift);
 251         writel(reg, &anatop->reg_core);
 252
 253         /*
 254          * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 255          * step
 256          */
 257         udelay(3 * step);
 258
 259         return 0;
 260 }
 261
 262 static void set_ahb_rate(u32 val)
 263 {
 264         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 265         u32 reg, div;
 266
 267         div = get_periph_clk() / val - 1;
 268         reg = readl(&mxc_ccm->cbcdr);
 269
 270         writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
 271                 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 272 }
 273
 274 static void clear_mmdc_ch_mask(void)
 275 {
 276         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 277         u32 reg;
 278         reg = readl(&mxc_ccm->ccdr);
 279
 280         /* Clear MMDC channel mask */
 281         reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 282         writel(reg, &mxc_ccm->ccdr);
 283 }
 284
 285 static void init_bandgap(void)
 286 {
 287         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 288         /*
 289          * Ensure the bandgap has stabilized.
 290          */
 291         while (!(readl(&anatop->ana_misc0) & 0x80))
 292                 ;
 293         /*
 294          * For best noise performance of the analog blocks using the
 295          * outputs of the bandgap, the reftop_selfbiasoff bit should
 296          * be set.
 297          */
 298         writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
 299 }
 300
 301
 302 #ifdef CONFIG_MX6SL
 303 static void set_preclk_from_osc(void)
 304 {
 305         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 306         u32 reg;
 307
 308         reg = readl(&mxc_ccm->cscmr1);
 309         reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
 310         writel(reg, &mxc_ccm->cscmr1);
 311 }
 312 #endif
 313
 314 int arch_cpu_init(void)
 315 {
 316         init_aips();
 317
 318         /* Need to clear MMDC_CHx_MASK to make warm reset work. */
 319         clear_mmdc_ch_mask();
 320
 321         /*
 322          * Disable self-bias circuit in the analog bandap.
 323          * The self-bias circuit is used by the bandgap during startup.
 324          * This bit should be set after the bandgap has initialized.
 325          */
 326         init_bandgap();
 327
 328         /*
 329          * When low freq boot is enabled, ROM will not set AHB
 330          * freq, so we need to ensure AHB freq is 132MHz in such
 331          * scenario.
 332          */
 333         if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
 334                 set_ahb_rate(132000000);
 335
 336                 /* Set perclk to source from OSC 24MHz */
 337 #if defined(CONFIG_MX6SL)
 338         set_preclk_from_osc();
 339 #endif
 340
 341         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 342
 343 #ifdef CONFIG_APBH_DMA
 344         /* Start APBH DMA */
 345         mxs_dma_init();
 346 #endif
 347
 348         init_src();
 349
 350         return 0;
 351 }
 352
 353 #ifdef CONFIG_ENV_IS_IN_MMC
 354 __weak int board_mmc_get_env_dev(int devno)
 355 {
 356         return CONFIG_SYS_MMC_ENV_DEV;
 357 }
 358
 359 static int mmc_get_boot_dev(void)
 360 {
 361         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 362         u32 soc_sbmr = readl(&src_regs->sbmr1);
 363         u32 bootsel;
 364         int devno;
 365
 366         /*
 367          * Refer to
 368          * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
 369          * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
 370          * i.MX6SL/SX/UL has same layout.
 371          */
 372         bootsel = (soc_sbmr & 0x000000FF) >> 6;
 373
 374         /* No boot from sd/mmc */
 375         if (bootsel != 1)
 376                 return -1;
 377
 378         /* BOOT_CFG2[3] and BOOT_CFG2[4] */
 379         devno = (soc_sbmr & 0x00001800) >> 11;
 380
 381         return devno;
 382 }
 383
 384 int mmc_get_env_dev(void)
 385 {
 386         int devno = mmc_get_boot_dev();
 387
 388         /* If not boot from sd/mmc, use default value */
 389         if (devno < 0)
 390                 return CONFIG_SYS_MMC_ENV_DEV;
 391
 392         return board_mmc_get_env_dev(devno);
 393 }
 394
 395 #ifdef CONFIG_SYS_MMC_ENV_PART
 396 __weak int board_mmc_get_env_part(int devno)
 397 {
 398         return CONFIG_SYS_MMC_ENV_PART;
 399 }
 400
 401 uint mmc_get_env_part(struct mmc *mmc)
 402 {
 403         int devno = mmc_get_boot_dev();
 404
 405         /* If not boot from sd/mmc, use default value */
 406         if (devno < 0)
 407                 return CONFIG_SYS_MMC_ENV_PART;
 408
 409         return board_mmc_get_env_part(devno);
 410 }
 411 #endif
 412 #endif
 413
 414 int board_postclk_init(void)
 415 {
 416         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 417
 418         return 0;
 419 }
 420
 421 #if defined(CONFIG_FEC_MXC)
 422 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 423 {
 424         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 425         struct fuse_bank *bank = &ocotp->bank[4];
 426         struct fuse_bank4_regs *fuse =
 427                         (struct fuse_bank4_regs *)bank->fuse_regs;
 428
 429         if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
 430                 dev_id == 1) {
 431                 u32 value = readl(&fuse->mac_addr2);
 432                 mac[0] = value >> 24 ;
 433                 mac[1] = value >> 16 ;
 434                 mac[2] = value >> 8 ;
 435                 mac[3] = value ;
 436
 437                 value = readl(&fuse->mac_addr1);
 438                 mac[4] = value >> 24 ;
 439                 mac[5] = value >> 16 ;
 440
 441         } else {
 442                 u32 value = readl(&fuse->mac_addr1);
 443                 mac[0] = (value >> 8);
 444                 mac[1] = value ;
 445
 446                 value = readl(&fuse->mac_addr0);
 447                 mac[2] = value >> 24 ;
 448                 mac[3] = value >> 16 ;
 449                 mac[4] = value >> 8 ;
 450                 mac[5] = value ;
 451         }
 452
 453 }
 454 #endif
 455
 456 /*
 457  * cfg_val will be used for
 458  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 459  * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 460  * instead of SBMR1 to determine the boot device.
 461  */
 462 const struct boot_mode soc_boot_modes[] = {
 463         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 464         /* reserved value should start rom usb */
 465         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 466         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 467         {"ecspi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 468         {"ecspi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 469         {"ecspi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 470         {"ecspi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 471         /* 4 bit bus width */
 472         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 473         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 474         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 475         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 476         {NULL,          0},
 477 };
 478
 479 void reset_misc(void)
 480 {
 481 #ifdef CONFIG_VIDEO_MXS
 482         lcdif_power_down();
 483 #endif
 484 }
 485
 486 void s_init(void)
 487 {
 488         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 489         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 490         u32 mask480;
 491         u32 mask528;
 492         u32 reg, periph1, periph2;
 493
 494         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
 495                 return;
 496
 497         /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 498          * to make sure PFD is working right, otherwise, PFDs may
 499          * not output clock after reset, MX6DL and MX6SL have added 396M pfd
 500          * workaround in ROM code, as bus clock need it
 501          */
 502
 503         mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
 504                 ANATOP_PFD_CLKGATE_MASK(1) |
 505                 ANATOP_PFD_CLKGATE_MASK(2) |
 506                 ANATOP_PFD_CLKGATE_MASK(3);
 507         mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
 508                 ANATOP_PFD_CLKGATE_MASK(3);
 509
 510         reg = readl(&ccm->cbcmr);
 511         periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
 512                 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
 513         periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
 514                 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
 515
 516         /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
 517         if ((periph2 != 0x2) && (periph1 != 0x2))
 518                 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
 519
 520         if ((periph2 != 0x1) && (periph1 != 0x1) &&
 521                 (periph2 != 0x3) && (periph1 != 0x3))
 522                 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 523
 524         writel(mask480, &anatop->pfd_480_set);
 525         writel(mask528, &anatop->pfd_528_set);
 526         writel(mask480, &anatop->pfd_480_clr);
 527         writel(mask528, &anatop->pfd_528_clr);
 528 }
 529
 530 #ifdef CONFIG_IMX_HDMI
 531 void imx_enable_hdmi_phy(void)
 532 {
 533         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 534         u8 reg;
 535         reg = readb(&hdmi->phy_conf0);
 536         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 537         writeb(reg, &hdmi->phy_conf0);
 538         udelay(3000);
 539         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 540         writeb(reg, &hdmi->phy_conf0);
 541         udelay(3000);
 542         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 543         writeb(reg, &hdmi->phy_conf0);
 544         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 545 }
 546
 547 void imx_setup_hdmi(void)
 548 {
 549         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 550         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 551         int reg;
 552
 553         /* Turn on HDMI PHY clock */
 554         reg = readl(&mxc_ccm->CCGR2);
 555         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 556                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 557         writel(reg, &mxc_ccm->CCGR2);
 558         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 559         reg = readl(&mxc_ccm->chsccdr);
 560         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 561                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 562                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 563         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 564                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 565                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 566                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 567         writel(reg, &mxc_ccm->chsccdr);
 568 }
 569 #endif
 570
 571 #ifdef CONFIG_IMX_BOOTAUX
 572 int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
 573 {
 574         struct src *src_reg;
 575         u32 stack, pc;
 576
 577         if (!boot_private_data)
 578                 return -EINVAL;
 579
 580         stack = *(u32 *)boot_private_data;
 581         pc = *(u32 *)(boot_private_data + 4);
 582
 583         /* Set the stack and pc to M4 bootROM */
 584         writel(stack, M4_BOOTROM_BASE_ADDR);
 585         writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 586
 587         /* Enable M4 */
 588         src_reg = (struct src *)SRC_BASE_ADDR;
 589         clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
 590                         SRC_SCR_M4_ENABLE_MASK);
 591
 592         return 0;
 593 }
 594
 595 int arch_auxiliary_core_check_up(u32 core_id)
 596 {
 597         struct src *src_reg = (struct src *)SRC_BASE_ADDR;
 598         unsigned val;
 599
 600         val = readl(&src_reg->scr);
 601
 602         if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
 603                 return 0;  /* assert in reset */
 604
 605         return 1;
 606 }
 607 #endif