arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/dma.h>
  18 #include <asm/imx-common/hab.h>
  19 #include <stdbool.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <dm.h>
  23 #include <imx_thermal.h>
  24
  25 enum ldo_reg {
  26         LDO_ARM,
  27         LDO_SOC,
  28         LDO_PU,
  29 };
  30
  31 struct scu_regs {
  32         u32     ctrl;
  33         u32     config;
  34         u32     status;
  35         u32     invalidate;
  36         u32     fpga_rev;
  37 };
  38
  39 #if defined(CONFIG_IMX_THERMAL)
  40 static const struct imx_thermal_plat imx6_thermal_plat = {
  41         .regs = (void *)ANATOP_BASE_ADDR,
  42         .fuse_bank = 1,
  43         .fuse_word = 6,
  44 };
  45
  46 U_BOOT_DEVICE(imx6_thermal) = {
  47         .name = "imx_thermal",
  48         .platdata = &imx6_thermal_plat,
  49 };
  50 #endif
  51
  52 #if defined(CONFIG_SECURE_BOOT)
  53 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  54         .bank = 0,
  55         .word = 6,
  56 };
  57 #endif
  58
  59 u32 get_nr_cpus(void)
  60 {
  61         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  62         return readl(&scu->config) & 3;
  63 }
  64
  65 u32 get_cpu_rev(void)
  66 {
  67         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  68         u32 reg = readl(&anatop->digprog_sololite);
  69         u32 type = ((reg >> 16) & 0xff);
  70         u32 major, cfg = 0;
  71
  72         if (type != MXC_CPU_MX6SL) {
  73                 reg = readl(&anatop->digprog);
  74                 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  75                 cfg = readl(&scu->config) & 3;
  76                 type = ((reg >> 16) & 0xff);
  77                 if (type == MXC_CPU_MX6DL) {
  78                         if (!cfg)
  79                                 type = MXC_CPU_MX6SOLO;
  80                 }
  81
  82                 if (type == MXC_CPU_MX6Q) {
  83                         if (cfg == 1)
  84                                 type = MXC_CPU_MX6D;
  85                 }
  86
  87         }
  88         major = ((reg >> 8) & 0xff);
  89         if ((major >= 1) &&
  90             ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  91                 major--;
  92                 type = MXC_CPU_MX6QP;
  93                 if (cfg == 1)
  94                         type = MXC_CPU_MX6DP;
  95         }
  96         reg &= 0xff;            /* mx6 silicon revision */
  97         return (type << 12) | (reg + (0x10 * (major + 1)));
  98 }
  99
 100 /*
 101  * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
 102  * defines a 2-bit SPEED_GRADING
 103  */
 104 #define OCOTP_CFG3_SPEED_SHIFT  16
 105 #define OCOTP_CFG3_SPEED_800MHZ 0
 106 #define OCOTP_CFG3_SPEED_850MHZ 1
 107 #define OCOTP_CFG3_SPEED_1GHZ   2
 108 #define OCOTP_CFG3_SPEED_1P2GHZ 3
 109
 110 u32 get_cpu_speed_grade_hz(void)
 111 {
 112         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 113         struct fuse_bank *bank = &ocotp->bank[0];
 114         struct fuse_bank0_regs *fuse =
 115                 (struct fuse_bank0_regs *)bank->fuse_regs;
 116         uint32_t val;
 117
 118         val = readl(&fuse->cfg3);
 119         val >>= OCOTP_CFG3_SPEED_SHIFT;
 120         val &= 0x3;
 121
 122         switch (val) {
 123         /* Valid for IMX6DQ */
 124         case OCOTP_CFG3_SPEED_1P2GHZ:
 125                 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 126                         return 1200000000;
 127         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 128         case OCOTP_CFG3_SPEED_1GHZ:
 129                 return 996000000;
 130         /* Valid for IMX6DQ */
 131         case OCOTP_CFG3_SPEED_850MHZ:
 132                 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
 133                         return 852000000;
 134         /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 135         case OCOTP_CFG3_SPEED_800MHZ:
 136                 return 792000000;
 137         }
 138         return 0;
 139 }
 140
 141 /*
 142  * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
 143  * defines a 2-bit Temperature Grade
 144  *
 145  * return temperature grade and min/max temperature in celcius
 146  */
 147 #define OCOTP_MEM0_TEMP_SHIFT          6
 148
 149 u32 get_cpu_temp_grade(int *minc, int *maxc)
 150 {
 151         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 152         struct fuse_bank *bank = &ocotp->bank[1];
 153         struct fuse_bank1_regs *fuse =
 154                 (struct fuse_bank1_regs *)bank->fuse_regs;
 155         uint32_t val;
 156
 157         val = readl(&fuse->mem0);
 158         val >>= OCOTP_MEM0_TEMP_SHIFT;
 159         val &= 0x3;
 160
 161         if (minc && maxc) {
 162                 if (val == TEMP_AUTOMOTIVE) {
 163                         *minc = -40;
 164                         *maxc = 125;
 165                 } else if (val == TEMP_INDUSTRIAL) {
 166                         *minc = -40;
 167                         *maxc = 105;
 168                 } else if (val == TEMP_EXTCOMMERCIAL) {
 169                         *minc = -20;
 170                         *maxc = 105;
 171                 } else {
 172                         *minc = 0;
 173                         *maxc = 95;
 174                 }
 175         }
 176         return val;
 177 }
 178
 179 #ifdef CONFIG_REVISION_TAG
 180 u32 __weak get_board_rev(void)
 181 {
 182         u32 cpurev = get_cpu_rev();
 183         u32 type = ((cpurev >> 12) & 0xff);
 184         if (type == MXC_CPU_MX6SOLO)
 185                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
 186
 187         if (type == MXC_CPU_MX6D)
 188                 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
 189
 190         return cpurev;
 191 }
 192 #endif
 193
 194 static void clear_ldo_ramp(void)
 195 {
 196         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 197         int reg;
 198
 199         /* ROM may modify LDO ramp up time according to fuse setting, so in
 200          * order to be in the safe side we neeed to reset these settings to
 201          * match the reset value: 0'b00
 202          */
 203         reg = readl(&anatop->ana_misc2);
 204         reg &= ~(0x3f << 24);
 205         writel(reg, &anatop->ana_misc2);
 206 }
 207
 208 /*
 209  * Set the PMU_REG_CORE register
 210  *
 211  * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 212  * Possible values are from 0.725V to 1.450V in steps of
 213  * 0.025V (25mV).
 214  */
 215 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 216 {
 217         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 218         u32 val, step, old, reg = readl(&anatop->reg_core);
 219         u8 shift;
 220
 221         if (mv < 725)
 222                 val = 0x00;     /* Power gated off */
 223         else if (mv > 1450)
 224                 val = 0x1F;     /* Power FET switched full on. No regulation */
 225         else
 226                 val = (mv - 700) / 25;
 227
 228         clear_ldo_ramp();
 229
 230         switch (ldo) {
 231         case LDO_SOC:
 232                 shift = 18;
 233                 break;
 234         case LDO_PU:
 235                 shift = 9;
 236                 break;
 237         case LDO_ARM:
 238                 shift = 0;
 239                 break;
 240         default:
 241                 return -EINVAL;
 242         }
 243
 244         old = (reg & (0x1F << shift)) >> shift;
 245         step = abs(val - old);
 246         if (step == 0)
 247                 return 0;
 248
 249         reg = (reg & ~(0x1F << shift)) | (val << shift);
 250         writel(reg, &anatop->reg_core);
 251
 252         /*
 253          * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 254          * step
 255          */
 256         udelay(3 * step);
 257
 258         return 0;
 259 }
 260
 261 static void set_ahb_rate(u32 val)
 262 {
 263         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 264         u32 reg, div;
 265
 266         div = get_periph_clk() / val - 1;
 267         reg = readl(&mxc_ccm->cbcdr);
 268
 269         writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
 270                 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 271 }
 272
 273 static void clear_mmdc_ch_mask(void)
 274 {
 275         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 276         u32 reg;
 277         reg = readl(&mxc_ccm->ccdr);
 278
 279         /* Clear MMDC channel mask */
 280         reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 281         writel(reg, &mxc_ccm->ccdr);
 282 }
 283
 284 static void init_bandgap(void)
 285 {
 286         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 287         /*
 288          * Ensure the bandgap has stabilized.
 289          */
 290         while (!(readl(&anatop->ana_misc0) & 0x80))
 291                 ;
 292         /*
 293          * For best noise performance of the analog blocks using the
 294          * outputs of the bandgap, the reftop_selfbiasoff bit should
 295          * be set.
 296          */
 297         writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
 298 }
 299
 300
 301 #ifdef CONFIG_MX6SL
 302 static void set_preclk_from_osc(void)
 303 {
 304         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 305         u32 reg;
 306
 307         reg = readl(&mxc_ccm->cscmr1);
 308         reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
 309         writel(reg, &mxc_ccm->cscmr1);
 310 }
 311 #endif
 312
 313 int arch_cpu_init(void)
 314 {
 315         init_aips();
 316
 317         /* Need to clear MMDC_CHx_MASK to make warm reset work. */
 318         clear_mmdc_ch_mask();
 319
 320         /*
 321          * Disable self-bias circuit in the analog bandap.
 322          * The self-bias circuit is used by the bandgap during startup.
 323          * This bit should be set after the bandgap has initialized.
 324          */
 325         init_bandgap();
 326
 327         /*
 328          * When low freq boot is enabled, ROM will not set AHB
 329          * freq, so we need to ensure AHB freq is 132MHz in such
 330          * scenario.
 331          */
 332         if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
 333                 set_ahb_rate(132000000);
 334
 335                 /* Set perclk to source from OSC 24MHz */
 336 #if defined(CONFIG_MX6SL)
 337         set_preclk_from_osc();
 338 #endif
 339
 340         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 341
 342 #ifdef CONFIG_APBH_DMA
 343         /* Start APBH DMA */
 344         mxs_dma_init();
 345 #endif
 346
 347         init_src();
 348
 349         return 0;
 350 }
 351
 352 int board_postclk_init(void)
 353 {
 354         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 355
 356         return 0;
 357 }
 358
 359 #if defined(CONFIG_FEC_MXC)
 360 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 361 {
 362         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 363         struct fuse_bank *bank = &ocotp->bank[4];
 364         struct fuse_bank4_regs *fuse =
 365                         (struct fuse_bank4_regs *)bank->fuse_regs;
 366
 367         u32 value = readl(&fuse->mac_addr_high);
 368         mac[0] = (value >> 8);
 369         mac[1] = value ;
 370
 371         value = readl(&fuse->mac_addr_low);
 372         mac[2] = value >> 24 ;
 373         mac[3] = value >> 16 ;
 374         mac[4] = value >> 8 ;
 375         mac[5] = value ;
 376
 377 }
 378 #endif
 379
 380 /*
 381  * cfg_val will be used for
 382  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 383  * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 384  * instead of SBMR1 to determine the boot device.
 385  */
 386 const struct boot_mode soc_boot_modes[] = {
 387         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 388         /* reserved value should start rom usb */
 389         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 390         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 391         {"ecspi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 392         {"ecspi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 393         {"ecspi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 394         {"ecspi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 395         /* 4 bit bus width */
 396         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 397         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 398         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 399         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 400         {NULL,          0},
 401 };
 402
 403 void reset_misc(void)
 404 {
 405 #ifdef CONFIG_VIDEO_MXS
 406         lcdif_power_down();
 407 #endif
 408 }
 409
 410 void s_init(void)
 411 {
 412         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 413         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 414         u32 mask480;
 415         u32 mask528;
 416         u32 reg, periph1, periph2;
 417
 418         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
 419                 return;
 420
 421         /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 422          * to make sure PFD is working right, otherwise, PFDs may
 423          * not output clock after reset, MX6DL and MX6SL have added 396M pfd
 424          * workaround in ROM code, as bus clock need it
 425          */
 426
 427         mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
 428                 ANATOP_PFD_CLKGATE_MASK(1) |
 429                 ANATOP_PFD_CLKGATE_MASK(2) |
 430                 ANATOP_PFD_CLKGATE_MASK(3);
 431         mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
 432                 ANATOP_PFD_CLKGATE_MASK(3);
 433
 434         reg = readl(&ccm->cbcmr);
 435         periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
 436                 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
 437         periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
 438                 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
 439
 440         /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
 441         if ((periph2 != 0x2) && (periph1 != 0x2))
 442                 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
 443
 444         if ((periph2 != 0x1) && (periph1 != 0x1) &&
 445                 (periph2 != 0x3) && (periph1 != 0x3))
 446                 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 447
 448         writel(mask480, &anatop->pfd_480_set);
 449         writel(mask528, &anatop->pfd_528_set);
 450         writel(mask480, &anatop->pfd_480_clr);
 451         writel(mask528, &anatop->pfd_528_clr);
 452 }
 453
 454 #ifdef CONFIG_IMX_HDMI
 455 void imx_enable_hdmi_phy(void)
 456 {
 457         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 458         u8 reg;
 459         reg = readb(&hdmi->phy_conf0);
 460         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 461         writeb(reg, &hdmi->phy_conf0);
 462         udelay(3000);
 463         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 464         writeb(reg, &hdmi->phy_conf0);
 465         udelay(3000);
 466         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 467         writeb(reg, &hdmi->phy_conf0);
 468         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 469 }
 470
 471 void imx_setup_hdmi(void)
 472 {
 473         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 474         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 475         int reg;
 476
 477         /* Turn on HDMI PHY clock */
 478         reg = readl(&mxc_ccm->CCGR2);
 479         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 480                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 481         writel(reg, &mxc_ccm->CCGR2);
 482         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 483         reg = readl(&mxc_ccm->chsccdr);
 484         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 485                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 486                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 487         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 488                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 489                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 490                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 491         writel(reg, &mxc_ccm->chsccdr);
 492 }
 493 #endif