arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/armv7.h>
  12 #include <asm/pl310.h>
  13 #include <asm/errno.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/imx-common/boot_mode.h>
  19 #include <asm/imx-common/dma.h>
  20 #include <stdbool.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/crm_regs.h>
  23
  24 enum ldo_reg {
  25         LDO_ARM,
  26         LDO_SOC,
  27         LDO_PU,
  28 };
  29
  30 struct scu_regs {
  31         u32     ctrl;
  32         u32     config;
  33         u32     status;
  34         u32     invalidate;
  35         u32     fpga_rev;
  36 };
  37
  38 u32 get_nr_cpus(void)
  39 {
  40         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  41         return readl(&scu->config) & 3;
  42 }
  43
  44 u32 get_cpu_rev(void)
  45 {
  46         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  47         u32 reg = readl(&anatop->digprog_sololite);
  48         u32 type = ((reg >> 16) & 0xff);
  49
  50         if (type != MXC_CPU_MX6SL) {
  51                 reg = readl(&anatop->digprog);
  52                 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  53                 u32 cfg = readl(&scu->config) & 3;
  54                 type = ((reg >> 16) & 0xff);
  55                 if (type == MXC_CPU_MX6DL) {
  56                         if (!cfg)
  57                                 type = MXC_CPU_MX6SOLO;
  58                 }
  59
  60                 if (type == MXC_CPU_MX6Q) {
  61                         if (cfg == 1)
  62                                 type = MXC_CPU_MX6D;
  63                 }
  64
  65         }
  66         reg &= 0xff;            /* mx6 silicon revision */
  67         return (type << 12) | (reg + 0x10);
  68 }
  69
  70 #ifdef CONFIG_REVISION_TAG
  71 u32 __weak get_board_rev(void)
  72 {
  73         u32 cpurev = get_cpu_rev();
  74         u32 type = ((cpurev >> 12) & 0xff);
  75         if (type == MXC_CPU_MX6SOLO)
  76                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  77
  78         if (type == MXC_CPU_MX6D)
  79                 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  80
  81         return cpurev;
  82 }
  83 #endif
  84
  85 void init_aips(void)
  86 {
  87         struct aipstz_regs *aips1, *aips2;
  88 #ifdef CONFIG_MX6SX
  89         struct aipstz_regs *aips3;
  90 #endif
  91
  92         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  93         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  94 #ifdef CONFIG_MX6SX
  95         aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
  96 #endif
  97
  98         /*
  99          * Set all MPROTx to be non-bufferable, trusted for R/W,
 100          * not forced to user-mode.
 101          */
 102         writel(0x77777777, &aips1->mprot0);
 103         writel(0x77777777, &aips1->mprot1);
 104         writel(0x77777777, &aips2->mprot0);
 105         writel(0x77777777, &aips2->mprot1);
 106
 107         /*
 108          * Set all OPACRx to be non-bufferable, not require
 109          * supervisor privilege level for access,allow for
 110          * write access and untrusted master access.
 111          */
 112         writel(0x00000000, &aips1->opacr0);
 113         writel(0x00000000, &aips1->opacr1);
 114         writel(0x00000000, &aips1->opacr2);
 115         writel(0x00000000, &aips1->opacr3);
 116         writel(0x00000000, &aips1->opacr4);
 117         writel(0x00000000, &aips2->opacr0);
 118         writel(0x00000000, &aips2->opacr1);
 119         writel(0x00000000, &aips2->opacr2);
 120         writel(0x00000000, &aips2->opacr3);
 121         writel(0x00000000, &aips2->opacr4);
 122
 123 #ifdef CONFIG_MX6SX
 124         /*
 125          * Set all MPROTx to be non-bufferable, trusted for R/W,
 126          * not forced to user-mode.
 127          */
 128         writel(0x77777777, &aips3->mprot0);
 129         writel(0x77777777, &aips3->mprot1);
 130
 131         /*
 132          * Set all OPACRx to be non-bufferable, not require
 133          * supervisor privilege level for access,allow for
 134          * write access and untrusted master access.
 135          */
 136         writel(0x00000000, &aips3->opacr0);
 137         writel(0x00000000, &aips3->opacr1);
 138         writel(0x00000000, &aips3->opacr2);
 139         writel(0x00000000, &aips3->opacr3);
 140         writel(0x00000000, &aips3->opacr4);
 141 #endif
 142 }
 143
 144 static void clear_ldo_ramp(void)
 145 {
 146         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 147         int reg;
 148
 149         /* ROM may modify LDO ramp up time according to fuse setting, so in
 150          * order to be in the safe side we neeed to reset these settings to
 151          * match the reset value: 0'b00
 152          */
 153         reg = readl(&anatop->ana_misc2);
 154         reg &= ~(0x3f << 24);
 155         writel(reg, &anatop->ana_misc2);
 156 }
 157
 158 /*
 159  * Set the PMU_REG_CORE register
 160  *
 161  * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 162  * Possible values are from 0.725V to 1.450V in steps of
 163  * 0.025V (25mV).
 164  */
 165 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 166 {
 167         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 168         u32 val, step, old, reg = readl(&anatop->reg_core);
 169         u8 shift;
 170
 171         if (mv < 725)
 172                 val = 0x00;     /* Power gated off */
 173         else if (mv > 1450)
 174                 val = 0x1F;     /* Power FET switched full on. No regulation */
 175         else
 176                 val = (mv - 700) / 25;
 177
 178         clear_ldo_ramp();
 179
 180         switch (ldo) {
 181         case LDO_SOC:
 182                 shift = 18;
 183                 break;
 184         case LDO_PU:
 185                 shift = 9;
 186                 break;
 187         case LDO_ARM:
 188                 shift = 0;
 189                 break;
 190         default:
 191                 return -EINVAL;
 192         }
 193
 194         old = (reg & (0x1F << shift)) >> shift;
 195         step = abs(val - old);
 196         if (step == 0)
 197                 return 0;
 198
 199         reg = (reg & ~(0x1F << shift)) | (val << shift);
 200         writel(reg, &anatop->reg_core);
 201
 202         /*
 203          * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
 204          * step
 205          */
 206         udelay(3 * step);
 207
 208         return 0;
 209 }
 210
 211 static void imx_set_wdog_powerdown(bool enable)
 212 {
 213         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 214         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 215
 216         /* Write to the PDE (Power Down Enable) bit */
 217         writew(enable, &wdog1->wmcr);
 218         writew(enable, &wdog2->wmcr);
 219 }
 220
 221 static void set_ahb_rate(u32 val)
 222 {
 223         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 224         u32 reg, div;
 225
 226         div = get_periph_clk() / val - 1;
 227         reg = readl(&mxc_ccm->cbcdr);
 228
 229         writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
 230                 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
 231 }
 232
 233 static void clear_mmdc_ch_mask(void)
 234 {
 235         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 236
 237         /* Clear MMDC channel mask */
 238         writel(0, &mxc_ccm->ccdr);
 239 }
 240
 241 int arch_cpu_init(void)
 242 {
 243         init_aips();
 244
 245         /* Need to clear MMDC_CHx_MASK to make warm reset work. */
 246         clear_mmdc_ch_mask();
 247
 248         /*
 249          * When low freq boot is enabled, ROM will not set AHB
 250          * freq, so we need to ensure AHB freq is 132MHz in such
 251          * scenario.
 252          */
 253         if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
 254                 set_ahb_rate(132000000);
 255
 256         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 257
 258 #ifdef CONFIG_APBH_DMA
 259         /* Start APBH DMA */
 260         mxs_dma_init();
 261 #endif
 262
 263         return 0;
 264 }
 265
 266 int board_postclk_init(void)
 267 {
 268         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 269
 270         return 0;
 271 }
 272
 273 #ifndef CONFIG_SYS_DCACHE_OFF
 274 void enable_caches(void)
 275 {
 276         /* Avoid random hang when download by usb */
 277         invalidate_dcache_all();
 278         /* Enable D-cache. I-cache is already enabled in start.S */
 279         dcache_enable();
 280 }
 281 #endif
 282
 283 #if defined(CONFIG_FEC_MXC)
 284 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 285 {
 286         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 287         struct fuse_bank *bank = &ocotp->bank[4];
 288         struct fuse_bank4_regs *fuse =
 289                         (struct fuse_bank4_regs *)bank->fuse_regs;
 290
 291         u32 value = readl(&fuse->mac_addr_high);
 292         mac[0] = (value >> 8);
 293         mac[1] = value ;
 294
 295         value = readl(&fuse->mac_addr_low);
 296         mac[2] = value >> 24 ;
 297         mac[3] = value >> 16 ;
 298         mac[4] = value >> 8 ;
 299         mac[5] = value ;
 300
 301 }
 302 #endif
 303
 304 void boot_mode_apply(unsigned cfg_val)
 305 {
 306         unsigned reg;
 307         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 308         writel(cfg_val, &psrc->gpr9);
 309         reg = readl(&psrc->gpr10);
 310         if (cfg_val)
 311                 reg |= 1 << 28;
 312         else
 313                 reg &= ~(1 << 28);
 314         writel(reg, &psrc->gpr10);
 315 }
 316 /*
 317  * cfg_val will be used for
 318  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 319  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 320  * to SBMR1, which will determine the boot device.
 321  */
 322 const struct boot_mode soc_boot_modes[] = {
 323         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 324         /* reserved value should start rom usb */
 325         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 326         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 327         {"ecspi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 328         {"ecspi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 329         {"ecspi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 330         {"ecspi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 331         /* 4 bit bus width */
 332         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 333         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 334         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 335         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 336         {NULL,          0},
 337 };
 338
 339 void s_init(void)
 340 {
 341         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 342         int is_6q = is_cpu_type(MXC_CPU_MX6Q);
 343         u32 mask480;
 344         u32 mask528;
 345
 346
 347         if (is_cpu_type(MXC_CPU_MX6SX))
 348                 return;
 349
 350         /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 351          * to make sure PFD is working right, otherwise, PFDs may
 352          * not output clock after reset, MX6DL and MX6SL have added 396M pfd
 353          * workaround in ROM code, as bus clock need it
 354          */
 355
 356         mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
 357                 ANATOP_PFD_CLKGATE_MASK(1) |
 358                 ANATOP_PFD_CLKGATE_MASK(2) |
 359                 ANATOP_PFD_CLKGATE_MASK(3);
 360         mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
 361                 ANATOP_PFD_CLKGATE_MASK(1) |
 362                 ANATOP_PFD_CLKGATE_MASK(3);
 363
 364         /*
 365          * Don't reset PFD2 on DL/S
 366          */
 367         if (is_6q)
 368                 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
 369         writel(mask480, &anatop->pfd_480_set);
 370         writel(mask528, &anatop->pfd_528_set);
 371         writel(mask480, &anatop->pfd_480_clr);
 372         writel(mask528, &anatop->pfd_528_clr);
 373 }
 374
 375 #ifdef CONFIG_IMX_HDMI
 376 void imx_enable_hdmi_phy(void)
 377 {
 378         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 379         u8 reg;
 380         reg = readb(&hdmi->phy_conf0);
 381         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 382         writeb(reg, &hdmi->phy_conf0);
 383         udelay(3000);
 384         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 385         writeb(reg, &hdmi->phy_conf0);
 386         udelay(3000);
 387         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 388         writeb(reg, &hdmi->phy_conf0);
 389         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 390 }
 391
 392 void imx_setup_hdmi(void)
 393 {
 394         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 395         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 396         int reg;
 397
 398         /* Turn on HDMI PHY clock */
 399         reg = readl(&mxc_ccm->CCGR2);
 400         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 401                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 402         writel(reg, &mxc_ccm->CCGR2);
 403         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 404         reg = readl(&mxc_ccm->chsccdr);
 405         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 406                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 407                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 408         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 409                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 410                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 411                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 412         writel(reg, &mxc_ccm->chsccdr);
 413 }
 414 #endif
 415
 416 #ifndef CONFIG_SYS_L2CACHE_OFF
 417 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
 418 void v7_outer_cache_enable(void)
 419 {
 420         struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
 421         unsigned int val;
 422
 423 #if defined CONFIG_MX6SL
 424         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 425         val = readl(&iomux->gpr[11]);
 426         if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
 427                 /* L2 cache configured as OCRAM, reset it */
 428                 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
 429                 writel(val, &iomux->gpr[11]);
 430         }
 431 #endif
 432
 433         /* Must disable the L2 before changing the latency parameters */
 434         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 435
 436         writel(0x132, &pl310->pl310_tag_latency_ctrl);
 437         writel(0x132, &pl310->pl310_data_latency_ctrl);
 438
 439         val = readl(&pl310->pl310_prefetch_ctrl);
 440
 441         /* Turn on the L2 I/D prefetch */
 442         val |= 0x30000000;
 443
 444         /*
 445          * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
 446          * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
 447          * But according to ARM PL310 errata: 752271
 448          * ID: 752271: Double linefill feature can cause data corruption
 449          * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
 450          * Workaround: The only workaround to this erratum is to disable the
 451          * double linefill feature. This is the default behavior.
 452          */
 453
 454 #ifndef CONFIG_MX6Q
 455         val |= 0x40800000;
 456 #endif
 457         writel(val, &pl310->pl310_prefetch_ctrl);
 458
 459         val = readl(&pl310->pl310_power_ctrl);
 460         val |= L2X0_DYNAMIC_CLK_GATING_EN;
 461         val |= L2X0_STNDBY_MODE_EN;
 462         writel(val, &pl310->pl310_power_ctrl);
 463
 464         setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 465 }
 466
 467 void v7_outer_cache_disable(void)
 468 {
 469         struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
 470
 471         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 472 }
 473 #endif /* !CONFIG_SYS_L2CACHE_OFF */