arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/errno.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/imx-common/boot_mode.h>
  33 #include <asm/imx-common/dma.h>
  34 #include <stdbool.h>
  35
  36 struct scu_regs {
  37         u32     ctrl;
  38         u32     config;
  39         u32     status;
  40         u32     invalidate;
  41         u32     fpga_rev;
  42 };
  43
  44 u32 get_cpu_rev(void)
  45 {
  46         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  47         u32 reg = readl(&anatop->digprog_sololite);
  48         u32 type = ((reg >> 16) & 0xff);
  49
  50         if (type != MXC_CPU_MX6SL) {
  51                 reg = readl(&anatop->digprog);
  52                 type = ((reg >> 16) & 0xff);
  53                 if (type == MXC_CPU_MX6DL) {
  54                         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  55                         u32 cfg = readl(&scu->config) & 3;
  56
  57                         if (!cfg)
  58                                 type = MXC_CPU_MX6SOLO;
  59                 }
  60         }
  61         reg &= 0xff;            /* mx6 silicon revision */
  62         return (type << 12) | (reg + 0x10);
  63 }
  64
  65 #ifdef CONFIG_REVISION_TAG
  66 u32 __weak get_board_rev(void)
  67 {
  68         u32 cpurev = get_cpu_rev();
  69         u32 type = ((cpurev >> 12) & 0xff);
  70         if (type == MXC_CPU_MX6SOLO)
  71                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  72
  73         return cpurev;
  74 }
  75 #endif
  76
  77 void init_aips(void)
  78 {
  79         struct aipstz_regs *aips1, *aips2;
  80
  81         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  82         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  83
  84         /*
  85          * Set all MPROTx to be non-bufferable, trusted for R/W,
  86          * not forced to user-mode.
  87          */
  88         writel(0x77777777, &aips1->mprot0);
  89         writel(0x77777777, &aips1->mprot1);
  90         writel(0x77777777, &aips2->mprot0);
  91         writel(0x77777777, &aips2->mprot1);
  92
  93         /*
  94          * Set all OPACRx to be non-bufferable, not require
  95          * supervisor privilege level for access,allow for
  96          * write access and untrusted master access.
  97          */
  98         writel(0x00000000, &aips1->opacr0);
  99         writel(0x00000000, &aips1->opacr1);
 100         writel(0x00000000, &aips1->opacr2);
 101         writel(0x00000000, &aips1->opacr3);
 102         writel(0x00000000, &aips1->opacr4);
 103         writel(0x00000000, &aips2->opacr0);
 104         writel(0x00000000, &aips2->opacr1);
 105         writel(0x00000000, &aips2->opacr2);
 106         writel(0x00000000, &aips2->opacr3);
 107         writel(0x00000000, &aips2->opacr4);
 108 }
 109
 110 /*
 111  * Set the VDDSOC
 112  *
 113  * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 114  * them to the specified millivolt level.
 115  * Possible values are from 0.725V to 1.450V in steps of
 116  * 0.025V (25mV).
 117  */
 118 void set_vddsoc(u32 mv)
 119 {
 120         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 121         u32 val, reg = readl(&anatop->reg_core);
 122
 123         if (mv < 725)
 124                 val = 0x00;     /* Power gated off */
 125         else if (mv > 1450)
 126                 val = 0x1F;     /* Power FET switched full on. No regulation */
 127         else
 128                 val = (mv - 700) / 25;
 129
 130         /*
 131          * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 132          * and set them to the calculated value (0.7V + val * 0.25V)
 133          */
 134         reg = (reg & ~(0x1F << 18)) | (val << 18);
 135         writel(reg, &anatop->reg_core);
 136 }
 137
 138 static void imx_set_wdog_powerdown(bool enable)
 139 {
 140         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 141         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 142
 143         /* Write to the PDE (Power Down Enable) bit */
 144         writew(enable, &wdog1->wmcr);
 145         writew(enable, &wdog2->wmcr);
 146 }
 147
 148 int arch_cpu_init(void)
 149 {
 150         init_aips();
 151
 152         set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
 153
 154         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 155
 156 #ifdef CONFIG_APBH_DMA
 157         /* Start APBH DMA */
 158         mxs_dma_init();
 159 #endif
 160
 161         return 0;
 162 }
 163
 164 #ifndef CONFIG_SYS_DCACHE_OFF
 165 void enable_caches(void)
 166 {
 167         /* Enable D-cache. I-cache is already enabled in start.S */
 168         dcache_enable();
 169 }
 170 #endif
 171
 172 #if defined(CONFIG_FEC_MXC)
 173 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 174 {
 175         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 176         struct fuse_bank *bank = &ocotp->bank[4];
 177         struct fuse_bank4_regs *fuse =
 178                         (struct fuse_bank4_regs *)bank->fuse_regs;
 179
 180         u32 value = readl(&fuse->mac_addr_high);
 181         mac[0] = (value >> 8);
 182         mac[1] = value ;
 183
 184         value = readl(&fuse->mac_addr_low);
 185         mac[2] = value >> 24 ;
 186         mac[3] = value >> 16 ;
 187         mac[4] = value >> 8 ;
 188         mac[5] = value ;
 189
 190 }
 191 #endif
 192
 193 void boot_mode_apply(unsigned cfg_val)
 194 {
 195         unsigned reg;
 196         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 197         writel(cfg_val, &psrc->gpr9);
 198         reg = readl(&psrc->gpr10);
 199         if (cfg_val)
 200                 reg |= 1 << 28;
 201         else
 202                 reg &= ~(1 << 28);
 203         writel(reg, &psrc->gpr10);
 204 }
 205 /*
 206  * cfg_val will be used for
 207  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 208  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 209  * to SBMR1, which will determine the boot device.
 210  */
 211 const struct boot_mode soc_boot_modes[] = {
 212         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 213         /* reserved value should start rom usb */
 214         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 215         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 216         {"escpi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 217         {"escpi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 218         {"escpi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 219         {"escpi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 220         /* 4 bit bus width */
 221         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 222         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 223         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 224         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 225         {NULL,          0},
 226 };
 227
 228 void s_init(void)
 229 {
 230 }