arch/arm/cpu/armv7/omap-common/hwinit-common.c

   1 /*
   2  *
   3  * Common functions for OMAP4/5 based boards
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <spl.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/sizes.h>
  18 #include <asm/emif.h>
  19 #include <asm/omap_common.h>
  20 #include <linux/compiler.h>
  21 #include <asm/cache.h>
  22 #include <asm/system.h>
  23
  24 #define ARMV7_DCACHE_WRITEBACK  0xe
  25 #define ARMV7_DOMAIN_CLIENT     1
  26 #define ARMV7_DOMAIN_MASK       (0x3 << 0)
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
  31 {
  32         int i;
  33         struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
  34
  35         for (i = 0; i < size; i++, pad++)
  36                 writew(pad->val, base + pad->offset);
  37 }
  38
  39 static void set_mux_conf_regs(void)
  40 {
  41         switch (omap_hw_init_context()) {
  42         case OMAP_INIT_CONTEXT_SPL:
  43                 set_muxconf_regs_essential();
  44                 break;
  45         case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
  46 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
  47                 set_muxconf_regs_non_essential();
  48 #endif
  49                 break;
  50         case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  51         case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  52                 set_muxconf_regs_essential();
  53 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
  54                 set_muxconf_regs_non_essential();
  55 #endif
  56                 break;
  57         }
  58 }
  59
  60 u32 cortex_rev(void)
  61 {
  62
  63         unsigned int rev;
  64
  65         /* Read Main ID Register (MIDR) */
  66         asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  67
  68         return rev;
  69 }
  70
  71 static void omap_rev_string(void)
  72 {
  73         u32 omap_rev = omap_revision();
  74         u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
  75         u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
  76         u32 major_rev = (omap_rev & 0x00000F00) >> 8;
  77         u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
  78
  79         if (soc_variant)
  80                 printf("OMAP");
  81         else
  82                 printf("DRA");
  83         printf("%x ES%x.%x\n", omap_variant, major_rev,
  84                minor_rev);
  85 }
  86
  87 #ifdef CONFIG_SPL_BUILD
  88 void spl_display_print(void)
  89 {
  90         omap_rev_string();
  91 }
  92 #endif
  93
  94 void __weak srcomp_enable(void)
  95 {
  96 }
  97
  98 #ifdef CONFIG_ARCH_CPU_INIT
  99 /*
 100  * SOC specific cpu init
 101  */
 102 int arch_cpu_init(void)
 103 {
 104         save_omap_boot_params();
 105         return 0;
 106 }
 107 #endif /* CONFIG_ARCH_CPU_INIT */
 108
 109 /*
 110  * Routine: s_init
 111  * Description: Does early system init of watchdog, muxing,  andclocks
 112  * Watchdog disable is done always. For the rest what gets done
 113  * depends on the boot mode in which this function is executed
 114  *   1. s_init of SPL running from SRAM
 115  *   2. s_init of U-Boot running from FLASH
 116  *   3. s_init of U-Boot loaded to SDRAM by SPL
 117  *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
 118  *      Configuration Header feature
 119  * Please have a look at the respective functions to see what gets
 120  * done in each of these cases
 121  * This function is called with SRAM stack.
 122  */
 123 void s_init(void)
 124 {
 125         /*
 126          * Save the boot parameters passed from romcode.
 127          * We cannot delay the saving further than this,
 128          * to prevent overwrites.
 129          */
 130 #ifdef CONFIG_SPL_BUILD
 131         save_omap_boot_params();
 132 #endif
 133         init_omap_revision();
 134         hw_data_init();
 135
 136 #ifdef CONFIG_SPL_BUILD
 137         if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
 138                 force_emif_self_refresh();
 139 #endif
 140         watchdog_init();
 141         set_mux_conf_regs();
 142 #ifdef CONFIG_SPL_BUILD
 143         srcomp_enable();
 144         setup_clocks_for_console();
 145
 146         gd = &gdata;
 147
 148         preloader_console_init();
 149         do_io_settings();
 150 #endif
 151         prcm_init();
 152 #ifdef CONFIG_SPL_BUILD
 153         /* For regular u-boot sdram_init() is called from dram_init() */
 154         sdram_init();
 155 #endif
 156 }
 157
 158 /*
 159  * Routine: wait_for_command_complete
 160  * Description: Wait for posting to finish on watchdog
 161  */
 162 void wait_for_command_complete(struct watchdog *wd_base)
 163 {
 164         int pending = 1;
 165         do {
 166                 pending = readl(&wd_base->wwps);
 167         } while (pending);
 168 }
 169
 170 /*
 171  * Routine: watchdog_init
 172  * Description: Shut down watch dogs
 173  */
 174 void watchdog_init(void)
 175 {
 176         struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
 177
 178         writel(WD_UNLOCK1, &wd2_base->wspr);
 179         wait_for_command_complete(wd2_base);
 180         writel(WD_UNLOCK2, &wd2_base->wspr);
 181 }
 182
 183
 184 /*
 185  * This function finds the SDRAM size available in the system
 186  * based on DMM section configurations
 187  * This is needed because the size of memory installed may be
 188  * different on different versions of the board
 189  */
 190 u32 omap_sdram_size(void)
 191 {
 192         u32 section, i, valid;
 193         u64 sdram_start = 0, sdram_end = 0, addr,
 194             size, total_size = 0, trap_size = 0;
 195
 196         for (i = 0; i < 4; i++) {
 197                 section = __raw_readl(DMM_BASE + i*4);
 198                 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
 199                         (EMIF_SDRC_ADDRSPC_SHIFT);
 200                 addr = section & EMIF_SYS_ADDR_MASK;
 201
 202                 /* See if the address is valid */
 203                 if ((addr >= DRAM_ADDR_SPACE_START) &&
 204                     (addr < DRAM_ADDR_SPACE_END)) {
 205                         size = ((section & EMIF_SYS_SIZE_MASK) >>
 206                                    EMIF_SYS_SIZE_SHIFT);
 207                         size = 1 << size;
 208                         size *= SZ_16M;
 209
 210                         if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
 211                                 if (!sdram_start || (addr < sdram_start))
 212                                         sdram_start = addr;
 213                                 if (!sdram_end || ((addr + size) > sdram_end))
 214                                         sdram_end = addr + size;
 215                         } else {
 216                                 trap_size = size;
 217                         }
 218
 219                 }
 220
 221         }
 222         total_size = (sdram_end - sdram_start) - (trap_size);
 223
 224         return total_size;
 225 }
 226
 227
 228 /*
 229  * Routine: dram_init
 230  * Description: sets uboots idea of sdram size
 231  */
 232 int dram_init(void)
 233 {
 234         sdram_init();
 235         gd->ram_size = omap_sdram_size();
 236         return 0;
 237 }
 238
 239 /*
 240  * Print board information
 241  */
 242 int checkboard(void)
 243 {
 244         puts(sysinfo.board_string);
 245         return 0;
 246 }
 247
 248 /*
 249  *  get_device_type(): tell if GP/HS/EMU/TST
 250  */
 251 u32 get_device_type(void)
 252 {
 253         return (readl((*ctrl)->control_status) &
 254                                       (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 255 }
 256
 257 /*
 258  * Print CPU information
 259  */
 260 int print_cpuinfo(void)
 261 {
 262         puts("CPU  : ");
 263         omap_rev_string();
 264
 265         return 0;
 266 }
 267 #ifndef CONFIG_SYS_DCACHE_OFF
 268 void enable_caches(void)
 269 {
 270         /* Enable D-cache. I-cache is already enabled in start.S */
 271         dcache_enable();
 272 }
 273
 274 void dram_bank_mmu_setup(int bank)
 275 {
 276         bd_t *bd = gd->bd;
 277         int     i;
 278
 279         u32 start = bd->bi_dram[bank].start >> 20;
 280         u32 size = bd->bi_dram[bank].size >> 20;
 281         u32 end = start + size;
 282
 283         debug("%s: bank: %d\n", __func__, bank);
 284         for (i = start; i < end; i++)
 285                 set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
 286
 287 }
 288
 289 void arm_init_domains(void)
 290 {
 291         u32 reg;
 292
 293         reg = get_dacr();
 294         /*
 295         * Set DOMAIN to client access so that all permissions
 296         * set in pagetables are validated by the mmu.
 297         */
 298         reg &= ~ARMV7_DOMAIN_MASK;
 299         reg |= ARMV7_DOMAIN_CLIENT;
 300         set_dacr(reg);
 301 }
 302 #endif