5 * Texas Instruments, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/errno.h>
16 #include "pipe3-phy.h"
18 /* PLLCTRL Registers */
19 #define PLL_STATUS 0x00000004
20 #define PLL_GO 0x00000008
21 #define PLL_CONFIGURATION1 0x0000000C
22 #define PLL_CONFIGURATION2 0x00000010
23 #define PLL_CONFIGURATION3 0x00000014
24 #define PLL_CONFIGURATION4 0x00000020
26 #define PLL_REGM_MASK 0x001FFE00
27 #define PLL_REGM_SHIFT 9
28 #define PLL_REGM_F_MASK 0x0003FFFF
29 #define PLL_REGM_F_SHIFT 0
30 #define PLL_REGN_MASK 0x000001FE
31 #define PLL_REGN_SHIFT 1
32 #define PLL_SELFREQDCO_MASK 0x0000000E
33 #define PLL_SELFREQDCO_SHIFT 1
34 #define PLL_SD_MASK 0x0003FC00
35 #define PLL_SD_SHIFT 10
36 #define SET_PLL_GO 0x1
37 #define PLL_TICOPWDN BIT(16)
38 #define PLL_LDOPWDN BIT(15)
42 /* PHY POWER CONTROL Register */
43 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
44 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
46 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
47 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
49 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
50 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
53 #define PLL_IDLE_TIME 100 /* in milliseconds */
54 #define PLL_LOCK_TIME 100 /* in milliseconds */
56 static inline u32
omap_pipe3_readl(void __iomem
*addr
, unsigned offset
)
58 return __raw_readl(addr
+ offset
);
61 static inline void omap_pipe3_writel(void __iomem
*addr
, unsigned offset
,
64 __raw_writel(data
, addr
+ offset
);
67 static struct pipe3_dpll_params
*omap_pipe3_get_dpll_params(struct omap_pipe3
71 struct pipe3_dpll_map
*dpll_map
= pipe3
->dpll_map
;
73 rate
= get_sys_clk_freq();
75 for (; dpll_map
->rate
; dpll_map
++) {
76 if (rate
== dpll_map
->rate
)
77 return &dpll_map
->params
;
80 printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
86 static int omap_pipe3_wait_lock(struct omap_pipe3
*phy
)
89 int timeout
= PLL_LOCK_TIME
;
93 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
98 if (!(val
& PLL_LOCK
)) {
99 printf("%s: DPLL failed to lock\n", __func__
);
106 static int omap_pipe3_dpll_program(struct omap_pipe3
*phy
)
109 struct pipe3_dpll_params
*dpll_params
;
111 dpll_params
= omap_pipe3_get_dpll_params(phy
);
113 printf("%s: Invalid DPLL parameters\n", __func__
);
117 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
118 val
&= ~PLL_REGN_MASK
;
119 val
|= dpll_params
->n
<< PLL_REGN_SHIFT
;
120 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
122 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
123 val
&= ~PLL_SELFREQDCO_MASK
;
124 val
|= dpll_params
->freq
<< PLL_SELFREQDCO_SHIFT
;
125 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
127 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
128 val
&= ~PLL_REGM_MASK
;
129 val
|= dpll_params
->m
<< PLL_REGM_SHIFT
;
130 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
132 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
);
133 val
&= ~PLL_REGM_F_MASK
;
134 val
|= dpll_params
->mf
<< PLL_REGM_F_SHIFT
;
135 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
, val
);
137 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
);
139 val
|= dpll_params
->sd
<< PLL_SD_SHIFT
;
140 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
, val
);
142 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_GO
, SET_PLL_GO
);
144 return omap_pipe3_wait_lock(phy
);
147 static void omap_control_phy_power(struct omap_pipe3
*phy
, int on
)
151 val
= readl(phy
->power_reg
);
153 rate
= get_sys_clk_freq();
157 val
&= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK
|
158 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK
);
159 val
|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON
<<
160 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT
;
162 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT
;
164 val
&= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK
;
165 val
|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF
<<
166 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT
;
169 writel(val
, phy
->power_reg
);
172 int phy_pipe3_power_on(struct omap_pipe3
*phy
)
177 /* Program the DPLL only if not locked */
178 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
179 if (!(val
& PLL_LOCK
)) {
180 ret
= omap_pipe3_dpll_program(phy
);
184 /* else just bring it out of IDLE mode */
185 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
186 if (val
& PLL_IDLE
) {
188 omap_pipe3_writel(phy
->pll_ctrl_base
,
189 PLL_CONFIGURATION2
, val
);
190 ret
= omap_pipe3_wait_lock(phy
);
196 /* Power up the PHY */
197 omap_control_phy_power(phy
, 1);
202 int phy_pipe3_power_off(struct omap_pipe3
*phy
)
205 int timeout
= PLL_IDLE_TIME
;
207 /* Power down the PHY */
208 omap_control_phy_power(phy
, 0);
210 /* Put DPLL in IDLE mode */
211 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
213 omap_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
215 /* wait for LDO and Oscillator to power down */
218 val
= omap_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
219 if ((val
& PLL_TICOPWDN
) && (val
& PLL_LDOPWDN
))
223 if (!(val
& PLL_TICOPWDN
) || !(val
& PLL_LDOPWDN
)) {
224 printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",