arch/arm/cpu/armv7/omap-common/sata.c

   1 /*
   2  * TI SATA platform driver
   3  *
   4  * (C) Copyright 2013
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <ahci.h>
  12 #include <scsi.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sata.h>
  15 #include <sata.h>
  16 #include <asm/io.h>
  17 #include "pipe3-phy.h"
  18
  19 static struct pipe3_dpll_map dpll_map_sata[] = {
  20         {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
  21         {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
  22         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
  23         {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
  24         {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
  25         {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
  26         { },                                    /* Terminator */
  27 };
  28
  29 struct omap_pipe3 sata_phy = {
  30         .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
  31         /* .power_reg is updated at runtime */
  32         .dpll_map = dpll_map_sata,
  33 };
  34
  35 int init_sata(int dev)
  36 {
  37         int ret;
  38         u32 val;
  39
  40         u32 const clk_domains_sata[] = {
  41                 0
  42         };
  43
  44         u32 const clk_modules_hw_auto_sata[] = {
  45                 (*prcm)->cm_l3init_ocp2scp3_clkctrl,
  46                 0
  47         };
  48
  49         u32 const clk_modules_explicit_en_sata[] = {
  50                 (*prcm)->cm_l3init_sata_clkctrl,
  51                 0
  52         };
  53
  54         do_enable_clocks(clk_domains_sata,
  55                          clk_modules_hw_auto_sata,
  56                          clk_modules_explicit_en_sata,
  57                          0);
  58
  59         /* Enable optional functional clock for SATA */
  60         setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
  61                      SATA_CLKCTRL_OPTFCLKEN_MASK);
  62
  63         sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
  64
  65         /* Power up the PHY */
  66         phy_pipe3_power_on(&sata_phy);
  67
  68         /* Enable SATA module, No Idle, No Standby */
  69         val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
  70         writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
  71
  72         ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
  73
  74         return ret;
  75 }
  76
  77 int reset_sata(int dev)
  78 {
  79         return 0;
  80 }
  81
  82 /* On OMAP platforms SATA provides the SCSI subsystem */
  83 void scsi_init(void)
  84 {
  85         init_sata(0);
  86         scsi_scan(1);
  87 }
  88
  89 void scsi_bus_reset(void)
  90 {
  91         ahci_reset((void __iomem *)DWC_AHSATA_BASE);
  92         ahci_init((void __iomem *)DWC_AHSATA_BASE);
  93 }