arch/arm/cpu/armv7/omap3/board.c

   1 /*
   2  *
   3  * Common board functions for OMAP3 based boards.
   4  *
   5  * (C) Copyright 2004-2008
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Sunil Kumar <sunilsaini05@gmail.com>
  10  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
  11  *
  12  * Derived from Beagle Board and 3430 SDP code by
  13  *      Richard Woodruff <r-woodruff2@ti.com>
  14  *      Syed Mohammed Khasim <khasim@ti.com>
  15  *
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35 #include <common.h>
  36 #include <spl.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/sys_proto.h>
  39 #include <asm/arch/mem.h>
  40 #include <asm/cache.h>
  41 #include <asm/armv7.h>
  42 #include <asm/arch/gpio.h>
  43 #include <asm/omap_common.h>
  44 #include <asm/arch/mmc_host_def.h>
  45 #include <i2c.h>
  46 #include <linux/compiler.h>
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 /* Declarations */
  51 extern omap3_sysinfo sysinfo;
  52 static void omap3_setup_aux_cr(void);
  53 #ifndef CONFIG_SYS_L2CACHE_OFF
  54 static void omap3_invalidate_l2_cache_secure(void);
  55 #endif
  56
  57 static const struct gpio_bank gpio_bank_34xx[6] = {
  58         { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
  59         { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
  60         { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
  61         { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
  62         { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
  63         { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
  64 };
  65
  66 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  67
  68 #ifdef CONFIG_SPL_BUILD
  69 /*
  70 * We use static variables because global data is not ready yet.
  71 * Initialized data is available in SPL right from the beginning.
  72 * We would not typically need to save these parameters in regular
  73 * U-Boot. This is needed only in SPL at the moment.
  74 */
  75 u32 omap3_boot_device = BOOT_DEVICE_NAND;
  76
  77 /* auto boot mode detection is not possible for OMAP3 - hard code */
  78 u32 spl_boot_mode(void)
  79 {
  80         switch (spl_boot_device()) {
  81         case BOOT_DEVICE_MMC2:
  82                 return MMCSD_MODE_RAW;
  83         case BOOT_DEVICE_MMC1:
  84                 return MMCSD_MODE_FAT;
  85                 break;
  86         default:
  87                 puts("spl: ERROR:  unknown device - can't select boot mode\n");
  88                 hang();
  89         }
  90 }
  91
  92 u32 spl_boot_device(void)
  93 {
  94         return omap3_boot_device;
  95 }
  96
  97 int board_mmc_init(bd_t *bis)
  98 {
  99         switch (spl_boot_device()) {
 100         case BOOT_DEVICE_MMC1:
 101                 omap_mmc_init(0, 0, 0);
 102                 break;
 103         case BOOT_DEVICE_MMC2:
 104         case BOOT_DEVICE_MMC2_2:
 105                 omap_mmc_init(1, 0, 0);
 106                 break;
 107         }
 108         return 0;
 109 }
 110
 111 void spl_board_init(void)
 112 {
 113 #ifdef CONFIG_SPL_NAND_SUPPORT
 114         gpmc_init();
 115 #endif
 116 #ifdef CONFIG_SPL_I2C_SUPPORT
 117         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 118 #endif
 119 }
 120 #endif /* CONFIG_SPL_BUILD */
 121
 122
 123 /******************************************************************************
 124  * Routine: secure_unlock
 125  * Description: Setup security registers for access
 126  *              (GP Device only)
 127  *****************************************************************************/
 128 void secure_unlock_mem(void)
 129 {
 130         struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
 131         struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
 132         struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
 133         struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
 134         struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 135
 136         /* Protection Module Register Target APE (PM_RT) */
 137         writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
 138         writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
 139         writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
 140         writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
 141
 142         writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
 143         writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
 144         writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
 145
 146         writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
 147         writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
 148         writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
 149         writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
 150
 151         /* IVA Changes */
 152         writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
 153         writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
 154         writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
 155
 156         /* SDRC region 0 public */
 157         writel(UNLOCK_1, &sms_base->rg_att0);
 158 }
 159
 160 /******************************************************************************
 161  * Routine: secureworld_exit()
 162  * Description: If chip is EMU and boot type is external
 163  *              configure secure registers and exit secure world
 164  *              general use.
 165  *****************************************************************************/
 166 void secureworld_exit()
 167 {
 168         unsigned long i;
 169
 170         /* configure non-secure access control register */
 171         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 172         /* enabling co-processor CP10 and CP11 accesses in NS world */
 173         __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
 174         /*
 175          * allow allocation of locked TLBs and L2 lines in NS world
 176          * allow use of PLE registers in NS world also
 177          */
 178         __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
 179         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
 180
 181         /* Enable ASA in ACR register */
 182         __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 183         __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
 184         __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
 185
 186         /* Exiting secure world */
 187         __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
 188         __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
 189         __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
 190 }
 191
 192 /******************************************************************************
 193  * Routine: try_unlock_sram()
 194  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 195  *              general use.
 196  *****************************************************************************/
 197 void try_unlock_memory()
 198 {
 199         int mode;
 200         int in_sdram = is_running_in_sdram();
 201
 202         /*
 203          * if GP device unlock device SRAM for general use
 204          * secure code breaks for Secure/Emulation device - HS/E/T
 205          */
 206         mode = get_device_type();
 207         if (mode == GP_DEVICE)
 208                 secure_unlock_mem();
 209
 210         /*
 211          * If device is EMU and boot is XIP external booting
 212          * Unlock firewalls and disable L2 and put chip
 213          * out of secure world
 214          *
 215          * Assuming memories are unlocked by the demon who put us in SDRAM
 216          */
 217         if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
 218             && (!in_sdram)) {
 219                 secure_unlock_mem();
 220                 secureworld_exit();
 221         }
 222
 223         return;
 224 }
 225
 226 /******************************************************************************
 227  * Routine: s_init
 228  * Description: Does early system init of muxing and clocks.
 229  *              - Called path is with SRAM stack.
 230  *****************************************************************************/
 231 void s_init(void)
 232 {
 233         int in_sdram = is_running_in_sdram();
 234
 235         watchdog_init();
 236
 237         try_unlock_memory();
 238
 239         /* Errata workarounds */
 240         omap3_setup_aux_cr();
 241
 242 #ifndef CONFIG_SYS_L2CACHE_OFF
 243         /* Invalidate L2-cache from secure mode */
 244         omap3_invalidate_l2_cache_secure();
 245 #endif
 246
 247         set_muxconf_regs();
 248         sdelay(100);
 249
 250         prcm_init();
 251
 252         per_clocks_enable();
 253
 254 #ifdef CONFIG_USB_EHCI_OMAP
 255         ehci_clocks_enable();
 256 #endif
 257
 258 #ifdef CONFIG_SPL_BUILD
 259         gd = &gdata;
 260
 261         preloader_console_init();
 262
 263         timer_init();
 264 #endif
 265
 266         if (!in_sdram)
 267                 mem_init();
 268 }
 269
 270 /*
 271  * Routine: misc_init_r
 272  * Description: A basic misc_init_r that just displays the die ID
 273  */
 274 int __weak misc_init_r(void)
 275 {
 276         dieid_num_r();
 277
 278         return 0;
 279 }
 280
 281 /******************************************************************************
 282  * Routine: wait_for_command_complete
 283  * Description: Wait for posting to finish on watchdog
 284  *****************************************************************************/
 285 void wait_for_command_complete(struct watchdog *wd_base)
 286 {
 287         int pending = 1;
 288         do {
 289                 pending = readl(&wd_base->wwps);
 290         } while (pending);
 291 }
 292
 293 /******************************************************************************
 294  * Routine: watchdog_init
 295  * Description: Shut down watch dogs
 296  *****************************************************************************/
 297 void watchdog_init(void)
 298 {
 299         struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
 300         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 301
 302         /*
 303          * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
 304          * either taken care of by ROM (HS/EMU) or not accessible (GP).
 305          * We need to take care of WD2-MPU or take a PRCM reset. WD3
 306          * should not be running and does not generate a PRCM reset.
 307          */
 308
 309         sr32(&prcm_base->fclken_wkup, 5, 1, 1);
 310         sr32(&prcm_base->iclken_wkup, 5, 1, 1);
 311         wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 312
 313         writel(WD_UNLOCK1, &wd2_base->wspr);
 314         wait_for_command_complete(wd2_base);
 315         writel(WD_UNLOCK2, &wd2_base->wspr);
 316 }
 317
 318 /******************************************************************************
 319  * Dummy function to handle errors for EABI incompatibility
 320  *****************************************************************************/
 321 void abort(void)
 322 {
 323 }
 324
 325 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
 326 /******************************************************************************
 327  * OMAP3 specific command to switch between NAND HW and SW ecc
 328  *****************************************************************************/
 329 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 330 {
 331         if (argc != 2)
 332                 goto usage;
 333         if (strncmp(argv[1], "hw", 2) == 0)
 334                 omap_nand_switch_ecc(1);
 335         else if (strncmp(argv[1], "sw", 2) == 0)
 336                 omap_nand_switch_ecc(0);
 337         else
 338                 goto usage;
 339
 340         return 0;
 341
 342 usage:
 343         printf ("Usage: nandecc %s\n", cmdtp->usage);
 344         return 1;
 345 }
 346
 347 U_BOOT_CMD(
 348         nandecc, 2, 1,  do_switch_ecc,
 349         "switch OMAP3 NAND ECC calculation algorithm",
 350         "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
 351 );
 352
 353 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
 354
 355 #ifdef CONFIG_DISPLAY_BOARDINFO
 356 /**
 357  * Print board information
 358  */
 359 int checkboard (void)
 360 {
 361         char *mem_s ;
 362
 363         if (is_mem_sdr())
 364                 mem_s = "mSDR";
 365         else
 366                 mem_s = "LPDDR";
 367
 368         printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
 369                         sysinfo.nand_string);
 370
 371         return 0;
 372 }
 373 #endif  /* CONFIG_DISPLAY_BOARDINFO */
 374
 375 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 376 {
 377         u32 i, num_params = *parameters;
 378         u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
 379
 380         /*
 381          * copy the parameters to an un-cached area to avoid coherency
 382          * issues
 383          */
 384         for (i = 0; i < num_params; i++) {
 385                 __raw_writel(*parameters, sram_scratch_space);
 386                 parameters++;
 387                 sram_scratch_space++;
 388         }
 389
 390         /* Now make the PPA call */
 391         do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 392 }
 393
 394 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 395 {
 396         u32 acr;
 397
 398         /* Read ACR */
 399         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 400         acr &= ~clear_bits;
 401         acr |= set_bits;
 402
 403         if (get_device_type() == GP_DEVICE) {
 404                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
 405                                        acr);
 406         } else {
 407                 struct emu_hal_params emu_romcode_params;
 408                 emu_romcode_params.num_params = 1;
 409                 emu_romcode_params.param1 = acr;
 410                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
 411                                        (u32 *)&emu_romcode_params);
 412         }
 413 }
 414
 415 static void omap3_setup_aux_cr(void)
 416 {
 417         /* Workaround for Cortex-A8 errata: #454179 #430973
 418          *      Set "IBE" bit
 419          *      Set "Disable Branch Size Mispredicts" bit
 420          * Workaround for erratum #621766
 421          *      Enable L1NEON bit
 422          * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
 423          */
 424         omap3_update_aux_cr_secure(0xE0, 0);
 425 }
 426
 427 #ifndef CONFIG_SYS_L2CACHE_OFF
 428 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 429 {
 430         u32 acr;
 431
 432         /* Read ACR */
 433         asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 434         acr &= ~clear_bits;
 435         acr |= set_bits;
 436
 437         /* Write ACR - affects non-secure banked bits */
 438         asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 439 }
 440
 441 /* Invalidate the entire L2 cache from secure mode */
 442 static void omap3_invalidate_l2_cache_secure(void)
 443 {
 444         if (get_device_type() == GP_DEVICE) {
 445                 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
 446                                       0);
 447         } else {
 448                 struct emu_hal_params emu_romcode_params;
 449                 emu_romcode_params.num_params = 1;
 450                 emu_romcode_params.param1 = 0;
 451                 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
 452                                        (u32 *)&emu_romcode_params);
 453         }
 454 }
 455
 456 void v7_outer_cache_enable(void)
 457 {
 458         /* Set L2EN */
 459         omap3_update_aux_cr_secure(0x2, 0);
 460
 461         /*
 462          * On some revisions L2EN bit is banked on some revisions it's not
 463          * No harm in setting both banked bits(in fact this is required
 464          * by an erratum)
 465          */
 466         omap3_update_aux_cr(0x2, 0);
 467 }
 468
 469 void omap3_outer_cache_disable(void)
 470 {
 471         /* Clear L2EN */
 472         omap3_update_aux_cr_secure(0, 0x2);
 473
 474         /*
 475          * On some revisions L2EN bit is banked on some revisions it's not
 476          * No harm in clearing both banked bits(in fact this is required
 477          * by an erratum)
 478          */
 479         omap3_update_aux_cr(0, 0x2);
 480 }
 481 #endif
 482
 483 #ifndef CONFIG_SYS_DCACHE_OFF
 484 void enable_caches(void)
 485 {
 486         /* Enable D-cache. I-cache is already enabled in start.S */
 487         dcache_enable();
 488 }
 489 #endif