arch/arm/cpu/armv7/omap3/emif4.c

   1 /*
   2  * Author :
   3  *     Vaibhav Hiremath <hvaibhav@ti.com>
   4  *
   5  * Based on mem.c and sdrc.c
   6  *
   7  * Copyright (C) 2010
   8  * Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/mem.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/emif4.h>
  31
  32 extern omap3_sysinfo sysinfo;
  33
  34 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
  35
  36 /*
  37  * is_mem_sdr -
  38  *  - Return 1 if mem type in use is SDR
  39  */
  40 u32 is_mem_sdr(void)
  41 {
  42         return 0;
  43 }
  44
  45 /*
  46  * get_sdr_cs_size -
  47  *  - Get size of chip select 0/1
  48  */
  49 u32 get_sdr_cs_size(u32 cs)
  50 {
  51         u32 size = 0;
  52
  53         /* TODO: Calculate the size based on EMIF4 configuration */
  54         if (cs == CS0)
  55                 size = CONFIG_SYS_CS0_SIZE;
  56
  57         return size;
  58 }
  59
  60 /*
  61  * get_sdr_cs_offset -
  62  *  - Get offset of cs from cs0 start
  63  */
  64 u32 get_sdr_cs_offset(u32 cs)
  65 {
  66         u32 offset = 0;
  67
  68         return offset;
  69 }
  70
  71 /*
  72  * do_emif4_init -
  73  *  - Init the emif4 module for DDR access
  74  *  - Early init routines, called from flash or SRAM.
  75  */
  76 void do_emif4_init(void)
  77 {
  78         unsigned int regval;
  79         /* Set the DDR PHY parameters in PHY ctrl registers */
  80         regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
  81                 EMIF4_DDR1_EXT_STRB_DIS);
  82         writel(regval, &emif4_base->ddr_phyctrl1);
  83         writel(regval, &emif4_base->ddr_phyctrl1_shdw);
  84         writel(0, &emif4_base->ddr_phyctrl2);
  85
  86         /* Reset the DDR PHY and wait till completed */
  87         regval = readl(&emif4_base->sdram_iodft_tlgc);
  88         regval |= (1<<10);
  89         writel(regval, &emif4_base->sdram_iodft_tlgc);
  90         /*Wait till that bit clears*/
  91         while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
  92         /*Re-verify the DDR PHY status*/
  93         while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
  94
  95         regval |= (1<<0);
  96         writel(regval, &emif4_base->sdram_iodft_tlgc);
  97         /* Set SDR timing registers */
  98         regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
  99                 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
 100                 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
 101                 EMIF4_TIM1_T_RP);
 102         writel(regval, &emif4_base->sdram_time1);
 103         writel(regval, &emif4_base->sdram_time1_shdw);
 104
 105         regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
 106                 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
 107                 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
 108         writel(regval, &emif4_base->sdram_time2);
 109         writel(regval, &emif4_base->sdram_time2_shdw);
 110
 111         regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
 112         writel(regval, &emif4_base->sdram_time3);
 113         writel(regval, &emif4_base->sdram_time3_shdw);
 114
 115         /* Set the PWR control register */
 116         regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
 117                 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
 118         writel(regval, &emif4_base->sdram_pwr_mgmt);
 119         writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
 120
 121         /* Set the DDR refresh rate control register */
 122         regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
 123         writel(regval, &emif4_base->sdram_refresh_ctrl);
 124         writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
 125
 126         /* set the SDRAM configuration register */
 127         regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
 128                 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
 129                 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
 130                 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
 131                 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
 132                 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
 133         writel(regval, &emif4_base->sdram_config);
 134 }
 135
 136 /*
 137  * dram_init -
 138  *  - Sets uboots idea of sdram size
 139  */
 140 int dram_init(void)
 141 {
 142         DECLARE_GLOBAL_DATA_PTR;
 143         unsigned int size0 = 0, size1 = 0;
 144
 145         size0 = get_sdr_cs_size(CS0);
 146         /*
 147          * If a second bank of DDR is attached to CS1 this is
 148          * where it can be started.  Early init code will init
 149          * memory on CS0.
 150          */
 151         if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
 152                 size1 = get_sdr_cs_size(CS1);
 153
 154         gd->ram_size = size0 + size1;
 155         return 0;
 156 }
 157
 158 void dram_init_banksize (void)
 159 {
 160         DECLARE_GLOBAL_DATA_PTR;
 161         unsigned int size0 = 0, size1 = 0;
 162
 163         size0 = get_sdr_cs_size(CS0);
 164         size1 = get_sdr_cs_size(CS1);
 165
 166         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 167         gd->bd->bi_dram[0].size = size0;
 168         gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 169         gd->bd->bi_dram[1].size = size1;
 170 }
 171
 172 /*
 173  * mem_init() -
 174  *  - Initialize memory subsystem
 175  */
 176 void mem_init(void)
 177 {
 178         do_emif4_init();
 179 }