arch/arm/cpu/armv7/omap3/sdrc.c

   1 /*
   2  * Functions related to OMAP3 SDRC.
   3  *
   4  * This file has been created after exctracting and consolidating
   5  * the SDRC related content from mem.c and board.c, also created
   6  * generic init function (mem_init).
   7  *
   8  * Copyright (C) 2004-2010
   9  * Texas Instruments Incorporated - http://www.ti.com/
  10  *
  11  * Author :
  12  *     Vaibhav Hiremath <hvaibhav@ti.com>
  13  *
  14  * Original implementation by (mem.c, board.c) :
  15  *      Sunil Kumar <sunilsaini05@gmail.com>
  16  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
  17  *      Manikandan Pillai <mani.pillai@ti.com>
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <asm/io.h>
  37 #include <asm/arch/mem.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 extern omap3_sysinfo sysinfo;
  41
  42 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  43
  44 /*
  45  * is_mem_sdr -
  46  *  - Return 1 if mem type in use is SDR
  47  */
  48 u32 is_mem_sdr(void)
  49 {
  50         if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
  51                 return 1;
  52         return 0;
  53 }
  54
  55 /*
  56  * make_cs1_contiguous -
  57  *  - For es2 and above remap cs1 behind cs0 to allow command line
  58  *    mem=xyz use all memory with out discontinuous support compiled in.
  59  *    Could do it at the ATAG, but there really is two banks...
  60  *  - Called as part of 2nd phase DDR init.
  61  */
  62 void make_cs1_contiguous(void)
  63 {
  64         u32 size, a_add_low, a_add_high;
  65
  66         size = get_sdr_cs_size(CS0);
  67         size >>= 25;    /* divide by 32 MiB to find size to offset CS1 */
  68         a_add_high = (size & 3) << 8;   /* set up low field */
  69         a_add_low = (size & 0x3C) >> 2; /* set up high field */
  70         writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
  71
  72 }
  73
  74
  75 /*
  76  * get_sdr_cs_size -
  77  *  - Get size of chip select 0/1
  78  */
  79 u32 get_sdr_cs_size(u32 cs)
  80 {
  81         u32 size;
  82
  83         /* get ram size field */
  84         size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
  85         size &= 0x3FF;          /* remove unwanted bits */
  86         size <<= 21;            /* multiply by 2 MiB to find size in MB */
  87         return size;
  88 }
  89
  90 /*
  91  * get_sdr_cs_offset -
  92  *  - Get offset of cs from cs0 start
  93  */
  94 u32 get_sdr_cs_offset(u32 cs)
  95 {
  96         u32 offset;
  97
  98         if (!cs)
  99                 return 0;
 100
 101         offset = readl(&sdrc_base->cs_cfg);
 102         offset = (offset & 15) << 27 | (offset & 0x30) << 17;
 103
 104         return offset;
 105 }
 106
 107 /*
 108  * do_sdrc_init -
 109  *  - Initialize the SDRAM for use.
 110  *  - code called once in C-Stack only context for CS0 and a possible 2nd
 111  *    time depending on memory configuration from stack+global context
 112  */
 113 void do_sdrc_init(u32 cs, u32 early)
 114 {
 115         struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
 116
 117         if (early) {
 118                 /* reset sdrc controller */
 119                 writel(SOFTRESET, &sdrc_base->sysconfig);
 120                 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
 121                                 12000000);
 122                 writel(0, &sdrc_base->sysconfig);
 123
 124                 /* setup sdrc to ball mux */
 125                 writel(SDRC_SHARING, &sdrc_base->sharing);
 126
 127                 /* Disable Power Down of CKE cuz of 1 CKE on combo part */
 128                 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
 129                                 &sdrc_base->power);
 130
 131                 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 132                 sdelay(0x20000);
 133         }
 134
 135         /*
 136          * SDRC timings are set up by x-load or config header
 137          * We don't need to redo them here.
 138          * Older x-loads configure only CS0
 139          * configure CS1 to handle this ommission
 140          */
 141         if (cs) {
 142                 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 143                 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 144                 writel(readl(&sdrc_base->cs[CS0].mcfg),
 145                         &sdrc_base->cs[CS1].mcfg);
 146                 writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
 147                         &sdrc_base->cs[CS1].rfr_ctrl);
 148                 writel(readl(&sdrc_actim_base0->ctrla),
 149                         &sdrc_actim_base1->ctrla);
 150                 writel(readl(&sdrc_actim_base0->ctrlb),
 151                         &sdrc_actim_base1->ctrlb);
 152
 153                 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
 154                 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
 155                 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
 156                 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
 157                 writel(readl(&sdrc_base->cs[CS0].mr),
 158                         &sdrc_base->cs[CS1].mr);
 159         }
 160
 161         /*
 162          * Test ram in this bank
 163          * Disable if bad or not present
 164          */
 165         if (!mem_ok(cs))
 166                 writel(0, &sdrc_base->cs[cs].mcfg);
 167 }
 168
 169 /*
 170  * dram_init -
 171  *  - Sets uboots idea of sdram size
 172  */
 173 int dram_init(void)
 174 {
 175         DECLARE_GLOBAL_DATA_PTR;
 176         unsigned int size0 = 0, size1 = 0;
 177
 178         size0 = get_sdr_cs_size(CS0);
 179         /*
 180          * If a second bank of DDR is attached to CS1 this is
 181          * where it can be started.  Early init code will init
 182          * memory on CS0.
 183          */
 184         if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
 185                 do_sdrc_init(CS1, NOT_EARLY);
 186                 make_cs1_contiguous();
 187
 188                 size1 = get_sdr_cs_size(CS1);
 189         }
 190         gd->ram_size = size0 + size1;
 191
 192         return 0;
 193 }
 194
 195 void dram_init_banksize (void)
 196 {
 197         DECLARE_GLOBAL_DATA_PTR;
 198         unsigned int size0 = 0, size1 = 0;
 199
 200         size0 = get_sdr_cs_size(CS0);
 201         size1 = get_sdr_cs_size(CS1);
 202
 203         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 204         gd->bd->bi_dram[0].size = size0;
 205         gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
 206         gd->bd->bi_dram[1].size = size1;
 207 }
 208
 209 /*
 210  * mem_init -
 211  *  - Init the sdrc chip,
 212  *  - Selects CS0 and CS1,
 213  */
 214 void mem_init(void)
 215 {
 216         /* only init up first bank here */
 217         do_sdrc_init(CS0, EARLY_INIT);
 218 }