3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/omap.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/omap_gpio.h>
22 struct prcm_regs
const **prcm
=
23 (struct prcm_regs
const **) OMAP_SRAM_SCRATCH_PRCM_PTR
;
24 struct dplls
const **dplls_data
=
25 (struct dplls
const **) OMAP_SRAM_SCRATCH_DPLLS_PTR
;
26 struct vcores_data
const **omap_vcores
=
27 (struct vcores_data
const **) OMAP_SRAM_SCRATCH_VCORES_PTR
;
28 struct omap_sys_ctrl_regs
const **ctrl
=
29 (struct omap_sys_ctrl_regs
const **)OMAP_SRAM_SCRATCH_SYS_CTRL
;
31 /* OPP HIGH FREQUENCY for ES2.0 */
32 static const struct dpll_params mpu_dpll_params_1_5ghz
[NUM_SYS_CLKS
] = {
33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
42 /* OPP NOM FREQUENCY for ES1.0 */
43 static const struct dpll_params mpu_dpll_params_800mhz
[NUM_SYS_CLKS
] = {
44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
53 /* OPP LOW FREQUENCY for ES1.0 */
54 static const struct dpll_params mpu_dpll_params_400mhz
[NUM_SYS_CLKS
] = {
55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
64 /* OPP LOW FREQUENCY for ES2.0 */
65 static const struct dpll_params mpu_dpll_params_499mhz
[NUM_SYS_CLKS
] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
76 static const struct dpll_params mpu_dpll_params_1ghz
[NUM_SYS_CLKS
] = {
77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
86 static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532
[NUM_SYS_CLKS
] = {
88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
97 static const struct dpll_params
98 core_dpll_params_2128mhz_ddr532_es2
[NUM_SYS_CLKS
] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
108 static const struct dpll_params
109 core_dpll_params_2128mhz_dra7xx
[NUM_SYS_CLKS
] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
119 static const struct dpll_params
120 core_dpll_params_2128mhz_ddr266
[NUM_SYS_CLKS
] = {
121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
130 static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2
[NUM_SYS_CLKS
] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
141 static const struct dpll_params per_dpll_params_768mhz
[NUM_SYS_CLKS
] = {
142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
151 static const struct dpll_params per_dpll_params_768mhz_es2
[NUM_SYS_CLKS
] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
161 static const struct dpll_params per_dpll_params_768mhz_dra7xx
[NUM_SYS_CLKS
] = {
162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
163 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
171 static const struct dpll_params iva_dpll_params_2330mhz
[NUM_SYS_CLKS
] = {
172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx
[NUM_SYS_CLKS
] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
191 /* ABE M & N values with sys_clk as source */
192 static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz
[NUM_SYS_CLKS
] = {
194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
203 /* ABE M & N values with 32K clock as source */
204 static const struct dpll_params abe_dpll_params_32k_196608khz
= {
205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
209 static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz
[NUM_SYS_CLKS
] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
220 static const struct dpll_params usb_dpll_params_1920mhz
[NUM_SYS_CLKS
] = {
221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
230 static const struct dpll_params ddr_dpll_params_2664mhz
[NUM_SYS_CLKS
] = {
231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
240 static const struct dpll_params ddr_dpll_params_2128mhz
[NUM_SYS_CLKS
] = {
241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
250 static const struct dpll_params gmac_dpll_params_2000mhz
[NUM_SYS_CLKS
] = {
251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
260 struct dplls omap5_dplls_es1
= {
261 .mpu
= mpu_dpll_params_800mhz
,
262 .core
= core_dpll_params_2128mhz_ddr532
,
263 .per
= per_dpll_params_768mhz
,
264 .iva
= iva_dpll_params_2330mhz
,
265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
266 .abe
= abe_dpll_params_sysclk_196608khz
,
268 .abe
= &abe_dpll_params_32k_196608khz
,
270 .usb
= usb_dpll_params_1920mhz
,
274 struct dplls omap5_dplls_es2
= {
275 .mpu
= mpu_dpll_params_1ghz
,
276 .core
= core_dpll_params_2128mhz_ddr532_es2
,
277 .per
= per_dpll_params_768mhz_es2
,
278 .iva
= iva_dpll_params_2330mhz
,
279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
280 .abe
= abe_dpll_params_sysclk_196608khz
,
282 .abe
= &abe_dpll_params_32k_196608khz
,
284 .usb
= usb_dpll_params_1920mhz
,
288 struct dplls dra7xx_dplls
= {
289 .mpu
= mpu_dpll_params_1ghz
,
290 .core
= core_dpll_params_2128mhz_dra7xx
,
291 .per
= per_dpll_params_768mhz_dra7xx
,
292 .abe
= abe_dpll_params_sysclk2_361267khz
,
293 .iva
= iva_dpll_params_2330mhz_dra7xx
,
294 .usb
= usb_dpll_params_1920mhz
,
295 .ddr
= ddr_dpll_params_2128mhz
,
296 .gmac
= gmac_dpll_params_2000mhz
,
299 struct dplls dra72x_dplls
= {
300 .mpu
= mpu_dpll_params_1ghz
,
301 .core
= core_dpll_params_2128mhz_dra7xx
,
302 .per
= per_dpll_params_768mhz_dra7xx
,
303 .abe
= abe_dpll_params_sysclk2_361267khz
,
304 .iva
= iva_dpll_params_2330mhz_dra7xx
,
305 .usb
= usb_dpll_params_1920mhz
,
306 .ddr
= ddr_dpll_params_2664mhz
,
307 .gmac
= gmac_dpll_params_2000mhz
,
310 struct pmic_data palmas
= {
311 .base_offset
= PALMAS_SMPS_BASE_VOLT_UV
,
312 .step
= 10000, /* 10 mV represented in uV */
314 * Offset codes 1-6 all give the base voltage in Palmas
315 * Offset code 0 switches OFF the SMPS
318 .i2c_slave_addr
= SMPS_I2C_SLAVE_ADDR
,
319 .pmic_bus_init
= sri2c_init
,
320 .pmic_write
= omap_vc_bypass_send_value
,
323 /* The TPS659038 and TPS65917 are software-compatible, use common struct */
324 struct pmic_data tps659038
= {
325 .base_offset
= PALMAS_SMPS_BASE_VOLT_UV
,
326 .step
= 10000, /* 10 mV represented in uV */
328 * Offset codes 1-6 all give the base voltage in Palmas
329 * Offset code 0 switches OFF the SMPS
332 .i2c_slave_addr
= TPS659038_I2C_SLAVE_ADDR
,
333 .pmic_bus_init
= gpi2c_init
,
334 .pmic_write
= palmas_i2c_write_u8
,
337 struct vcores_data omap5430_volts
= {
338 .mpu
.value
= VDD_MPU
,
339 .mpu
.addr
= SMPS_REG_ADDR_12_MPU
,
342 .core
.value
= VDD_CORE
,
343 .core
.addr
= SMPS_REG_ADDR_8_CORE
,
344 .core
.pmic
= &palmas
,
347 .mm
.addr
= SMPS_REG_ADDR_45_IVA
,
351 struct vcores_data omap5430_volts_es2
= {
352 .mpu
.value
= VDD_MPU_ES2
,
353 .mpu
.addr
= SMPS_REG_ADDR_12_MPU
,
356 .core
.value
= VDD_CORE_ES2
,
357 .core
.addr
= SMPS_REG_ADDR_8_CORE
,
358 .core
.pmic
= &palmas
,
360 .mm
.value
= VDD_MM_ES2
,
361 .mm
.addr
= SMPS_REG_ADDR_45_IVA
,
365 struct vcores_data dra752_volts
= {
366 .mpu
.value
= VDD_MPU_DRA752
,
367 .mpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_MPU_NOM
,
368 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
369 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
370 .mpu
.pmic
= &tps659038
,
372 .eve
.value
= VDD_EVE_DRA752
,
373 .eve
.efuse
.reg
= STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
374 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
375 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
376 .eve
.pmic
= &tps659038
,
378 .gpu
.value
= VDD_GPU_DRA752
,
379 .gpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_GPU_NOM
,
380 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
381 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
382 .gpu
.pmic
= &tps659038
,
384 .core
.value
= VDD_CORE_DRA752
,
385 .core
.efuse
.reg
= STD_FUSE_OPP_VMIN_CORE_NOM
,
386 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
387 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
388 .core
.pmic
= &tps659038
,
390 .iva
.value
= VDD_IVA_DRA752
,
391 .iva
.efuse
.reg
= STD_FUSE_OPP_VMIN_IVA_NOM
,
392 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
393 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
394 .iva
.pmic
= &tps659038
,
397 struct vcores_data dra722_volts
= {
398 .mpu
.value
= VDD_MPU_DRA72x
,
399 .mpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_MPU_NOM
,
400 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
401 .mpu
.addr
= TPS65917_REG_ADDR_SMPS1
,
402 .mpu
.pmic
= &tps659038
,
404 .core
.value
= VDD_CORE_DRA72x
,
405 .core
.efuse
.reg
= STD_FUSE_OPP_VMIN_CORE_NOM
,
406 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
407 .core
.addr
= TPS65917_REG_ADDR_SMPS2
,
408 .core
.pmic
= &tps659038
,
411 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
412 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
414 .gpu
.value
= VDD_GPU_DRA72x
,
415 .gpu
.efuse
.reg
= STD_FUSE_OPP_VMIN_GPU_NOM
,
416 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
417 .gpu
.addr
= TPS65917_REG_ADDR_SMPS3
,
418 .gpu
.pmic
= &tps659038
,
420 .eve
.value
= VDD_EVE_DRA72x
,
421 .eve
.efuse
.reg
= STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
422 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
423 .eve
.addr
= TPS65917_REG_ADDR_SMPS3
,
424 .eve
.pmic
= &tps659038
,
426 .iva
.value
= VDD_IVA_DRA72x
,
427 .iva
.efuse
.reg
= STD_FUSE_OPP_VMIN_IVA_NOM
,
428 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
429 .iva
.addr
= TPS65917_REG_ADDR_SMPS3
,
430 .iva
.pmic
= &tps659038
,
434 * Enable essential clock domains, modules and
435 * do some additional special settings needed
437 void enable_basic_clocks(void)
439 u32
const clk_domains_essential
[] = {
440 (*prcm
)->cm_l4per_clkstctrl
,
441 (*prcm
)->cm_l3init_clkstctrl
,
442 (*prcm
)->cm_memif_clkstctrl
,
443 (*prcm
)->cm_l4cfg_clkstctrl
,
444 #ifdef CONFIG_DRIVER_TI_CPSW
445 (*prcm
)->cm_gmac_clkstctrl
,
450 u32
const clk_modules_hw_auto_essential
[] = {
451 (*prcm
)->cm_l3_gpmc_clkctrl
,
452 (*prcm
)->cm_memif_emif_1_clkctrl
,
453 (*prcm
)->cm_memif_emif_2_clkctrl
,
454 (*prcm
)->cm_l4cfg_l4_cfg_clkctrl
,
455 (*prcm
)->cm_wkup_gpio1_clkctrl
,
456 (*prcm
)->cm_l4per_gpio2_clkctrl
,
457 (*prcm
)->cm_l4per_gpio3_clkctrl
,
458 (*prcm
)->cm_l4per_gpio4_clkctrl
,
459 (*prcm
)->cm_l4per_gpio5_clkctrl
,
460 (*prcm
)->cm_l4per_gpio6_clkctrl
,
461 (*prcm
)->cm_l4per_gpio7_clkctrl
,
462 (*prcm
)->cm_l4per_gpio8_clkctrl
,
463 #ifdef CONFIG_USB_DWC3
464 (*prcm
)->cm_l3init_ocp2scp1_clkctrl
,
465 (*prcm
)->cm_l3init_usb_otg_ss1_clkctrl
,
470 u32
const clk_modules_explicit_en_essential
[] = {
471 (*prcm
)->cm_wkup_gptimer1_clkctrl
,
472 (*prcm
)->cm_l3init_hsmmc1_clkctrl
,
473 (*prcm
)->cm_l3init_hsmmc2_clkctrl
,
474 (*prcm
)->cm_l4per_gptimer2_clkctrl
,
475 (*prcm
)->cm_wkup_wdtimer2_clkctrl
,
476 (*prcm
)->cm_l4per_uart3_clkctrl
,
477 (*prcm
)->cm_l4per_i2c1_clkctrl
,
478 #ifdef CONFIG_DRIVER_TI_CPSW
479 (*prcm
)->cm_gmac_gmac_clkctrl
,
482 #ifdef CONFIG_TI_QSPI
483 (*prcm
)->cm_l4per_qspi_clkctrl
,
488 /* Enable optional additional functional clock for GPIO4 */
489 setbits_le32((*prcm
)->cm_l4per_gpio4_clkctrl
,
490 GPIO4_CLKCTRL_OPTFCLKEN_MASK
);
492 /* Enable 96 MHz clock for MMC1 & MMC2 */
493 setbits_le32((*prcm
)->cm_l3init_hsmmc1_clkctrl
,
494 HSMMC_CLKCTRL_CLKSEL_MASK
);
495 setbits_le32((*prcm
)->cm_l3init_hsmmc2_clkctrl
,
496 HSMMC_CLKCTRL_CLKSEL_MASK
);
498 #ifdef CONFIG_USB_DWC3
499 /* Enable 960 MHz clock for dwc3 */
500 setbits_le32((*prcm
)->cm_l3init_usb_otg_ss1_clkctrl
,
501 OPTFCLKEN_REFCLK960M
);
503 /* Enable 32 KHz clock for dwc3 */
504 setbits_le32((*prcm
)->cm_coreaon_usb_phy1_core_clkctrl
,
505 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K
);
508 /* Set the correct clock dividers for mmc */
509 setbits_le32((*prcm
)->cm_l3init_hsmmc1_clkctrl
,
510 HSMMC_CLKCTRL_CLKSEL_DIV_MASK
);
511 setbits_le32((*prcm
)->cm_l3init_hsmmc2_clkctrl
,
512 HSMMC_CLKCTRL_CLKSEL_DIV_MASK
);
514 /* Select 32KHz clock as the source of GPTIMER1 */
515 setbits_le32((*prcm
)->cm_wkup_gptimer1_clkctrl
,
516 GPTIMER1_CLKCTRL_CLKSEL_MASK
);
518 do_enable_clocks(clk_domains_essential
,
519 clk_modules_hw_auto_essential
,
520 clk_modules_explicit_en_essential
,
523 #ifdef CONFIG_TI_QSPI
524 setbits_le32((*prcm
)->cm_l4per_qspi_clkctrl
, (1<<24));
527 /* Enable SCRM OPT clocks for PER and CORE dpll */
528 setbits_le32((*prcm
)->cm_wkupaon_scrm_clkctrl
,
529 OPTFCLKEN_SCRM_PER_MASK
);
530 setbits_le32((*prcm
)->cm_wkupaon_scrm_clkctrl
,
531 OPTFCLKEN_SCRM_CORE_MASK
);
534 void enable_basic_uboot_clocks(void)
536 u32
const clk_domains_essential
[] = {
540 u32
const clk_modules_hw_auto_essential
[] = {
541 (*prcm
)->cm_l3init_hsusbtll_clkctrl
,
545 u32
const clk_modules_explicit_en_essential
[] = {
546 (*prcm
)->cm_l4per_mcspi1_clkctrl
,
547 (*prcm
)->cm_l4per_i2c2_clkctrl
,
548 (*prcm
)->cm_l4per_i2c3_clkctrl
,
549 (*prcm
)->cm_l4per_i2c4_clkctrl
,
550 (*prcm
)->cm_l4per_i2c5_clkctrl
,
551 (*prcm
)->cm_l3init_hsusbhost_clkctrl
,
552 (*prcm
)->cm_l3init_fsusb_clkctrl
,
555 do_enable_clocks(clk_domains_essential
,
556 clk_modules_hw_auto_essential
,
557 clk_modules_explicit_en_essential
,
561 const struct ctrl_ioregs ioregs_omap5430
= {
562 .ctrl_ddrch
= DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN
,
563 .ctrl_lpddr2ch
= DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN
,
564 .ctrl_ddrio_0
= DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL
,
565 .ctrl_ddrio_1
= DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL
,
566 .ctrl_ddrio_2
= DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL
,
569 const struct ctrl_ioregs ioregs_omap5432_es1
= {
570 .ctrl_ddrch
= DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL
,
571 .ctrl_lpddr2ch
= 0x0,
572 .ctrl_ddr3ch
= DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL
,
573 .ctrl_ddrio_0
= DDR_IO_0_VREF_CELLS_DDR3_VALUE
,
574 .ctrl_ddrio_1
= DDR_IO_1_VREF_CELLS_DDR3_VALUE
,
575 .ctrl_ddrio_2
= DDR_IO_2_VREF_CELLS_DDR3_VALUE
,
576 .ctrl_emif_sdram_config_ext
= SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES
,
577 .ctrl_emif_sdram_config_ext_final
= SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES
,
580 const struct ctrl_ioregs ioregs_omap5432_es2
= {
581 .ctrl_ddrch
= DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2
,
582 .ctrl_lpddr2ch
= 0x0,
583 .ctrl_ddr3ch
= DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2
,
584 .ctrl_ddrio_0
= DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2
,
585 .ctrl_ddrio_1
= DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2
,
586 .ctrl_ddrio_2
= DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2
,
587 .ctrl_emif_sdram_config_ext
= SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES
,
588 .ctrl_emif_sdram_config_ext_final
= SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES
,
591 const struct ctrl_ioregs ioregs_dra7xx_es1
= {
592 .ctrl_ddrch
= 0x40404040,
593 .ctrl_lpddr2ch
= 0x40404040,
594 .ctrl_ddr3ch
= 0x80808080,
595 .ctrl_ddrio_0
= 0xA2084210,
596 .ctrl_ddrio_1
= 0x84210840,
597 .ctrl_ddrio_2
= 0x84210000,
598 .ctrl_emif_sdram_config_ext
= 0x0001C1A7,
599 .ctrl_emif_sdram_config_ext_final
= 0x0001C1A7,
600 .ctrl_ddr_ctrl_ext_0
= 0xA2000000,
603 const struct ctrl_ioregs ioregs_dra72x_es1
= {
604 .ctrl_ddrch
= 0x40404040,
605 .ctrl_lpddr2ch
= 0x40404040,
606 .ctrl_ddr3ch
= 0x60606080,
607 .ctrl_ddrio_0
= 0xA2084210,
608 .ctrl_ddrio_1
= 0x84210840,
609 .ctrl_ddrio_2
= 0x84210000,
610 .ctrl_emif_sdram_config_ext
= 0x0001C1A7,
611 .ctrl_emif_sdram_config_ext_final
= 0x0001C1A7,
612 .ctrl_ddr_ctrl_ext_0
= 0xA2000000,
615 void __weak
hw_data_init(void)
617 u32 omap_rev
= omap_revision();
623 *prcm
= &omap5_es1_prcm
;
624 *dplls_data
= &omap5_dplls_es1
;
625 *omap_vcores
= &omap5430_volts
;
631 *prcm
= &omap5_es2_prcm
;
632 *dplls_data
= &omap5_dplls_es2
;
633 *omap_vcores
= &omap5430_volts_es2
;
639 *prcm
= &dra7xx_prcm
;
640 *dplls_data
= &dra7xx_dplls
;
641 *omap_vcores
= &dra752_volts
;
642 *ctrl
= &dra7xx_ctrl
;
646 *prcm
= &dra7xx_prcm
;
647 *dplls_data
= &dra72x_dplls
;
648 *omap_vcores
= &dra722_volts
;
649 *ctrl
= &dra7xx_ctrl
;
653 printf("\n INVALID OMAP REVISION ");
657 void get_ioregs(const struct ctrl_ioregs
**regs
)
659 u32 omap_rev
= omap_revision();
664 *regs
= &ioregs_omap5430
;
667 *regs
= &ioregs_omap5432_es1
;
670 *regs
= &ioregs_omap5432_es2
;
674 *regs
= &ioregs_dra7xx_es1
;
677 *regs
= &ioregs_dra72x_es1
;
681 printf("\n INVALID OMAP REVISION ");