arch/arm/cpu/armv7/omap5/hw_data.c

   1 /*
   2  *
   3  * HW data initialization for OMAP5
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <palmas.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/omap_gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/emif.h>
  21
  22 struct prcm_regs const **prcm =
  23                         (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  24 struct dplls const **dplls_data =
  25                         (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  26 struct vcores_data const **omap_vcores =
  27                 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  28 struct omap_sys_ctrl_regs const **ctrl =
  29         (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  30
  31 /* OPP HIGH FREQUENCY for ES2.0 */
  32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  33         {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  34         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  35         {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  36         {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  37         {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  38         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  39         {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  40 };
  41
  42 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
  43 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
  44         {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  45         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  46         {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  47         {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 19.2 MHz */
  48         {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  49         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  50         {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}       /* 38.4 MHz */
  51 };
  52
  53 /* OPP NOM FREQUENCY for ES1.0 */
  54 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  55         {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  56         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  57         {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  58         {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  59         {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  60         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  61         {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  62 };
  63
  64 /* OPP LOW FREQUENCY for ES1.0 */
  65 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  66         {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
  67         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  68         {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
  69         {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  70         {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  71         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  72         {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  73 };
  74
  75 /* OPP LOW FREQUENCY for ES2.0 */
  76 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  77         {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
  78         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
  79         {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
  80         {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
  81         {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
  82         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  83         {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
  84 };
  85
  86 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  87         {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
  88         {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
  89         {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
  90         {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
  91         {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 26 MHz   */
  92         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
  93         {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 38.4 MHz */
  94 };
  95
  96 static const struct dpll_params
  97                         core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  98         {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 12 MHz   */
  99         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 100         {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 16.8 MHz */
 101         {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 19.2 MHz */
 102         {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},              /* 26 MHz   */
 103         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 104         {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}               /* 38.4 MHz */
 105 };
 106
 107 static const struct dpll_params
 108                         core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
 109         {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 12 MHz   */
 110         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 111         {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 16.8 MHz */
 112         {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 19.2 MHz */
 113         {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},               /* 26 MHz   */
 114         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 115         {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}                /* 38.4 MHz */
 116 };
 117
 118 static const struct dpll_params
 119                 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
 120         {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 12 MHz   */
 121         {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 20 MHz   */
 122         {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 16.8 MHz */
 123         {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 19.2 MHz */
 124         {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 26 MHz   */
 125         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 126         {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},              /* 38.4 MHz */
 127 };
 128
 129 static const struct dpll_params
 130                         core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
 131         {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 12 MHz   */
 132         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 133         {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 16.8 MHz */
 134         {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 19.2 MHz */
 135         {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},           /* 26 MHz   */
 136         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 137         {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}            /* 38.4 MHz */
 138 };
 139
 140 static const struct dpll_params
 141                         core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
 142         {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 12 MHz   */
 143         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 144         {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 16.8 MHz */
 145         {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 19.2 MHz */
 146         {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},            /* 26 MHz   */
 147         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 148         {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}             /* 38.4 MHz */
 149 };
 150
 151 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 152         {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 153         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 154         {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 155         {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 156         {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 157         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 158         {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 159 };
 160
 161 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 162         {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 12 MHz   */
 163         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 164         {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 165         {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 166         {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},           /* 26 MHz   */
 167         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 168         {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}              /* 38.4 MHz */
 169 };
 170
 171 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 172         {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
 173         {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
 174         {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
 175         {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
 176         {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
 177         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 178         {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
 179 };
 180
 181 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
 182         {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 183         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 184         {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 185         {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 186         {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 187         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 188         {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}           /* 38.4 MHz */
 189 };
 190
 191 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
 192         {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 193         {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz */
 194         {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 16.8 MHz */
 195         {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 196         {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 197         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 198         {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 38.4 MHz */
 199 };
 200
 201 /* ABE M & N values with sys_clk as source */
 202 static const struct dpll_params
 203                 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
 204         {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
 205         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
 206         {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 207         {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 19.2 MHz */
 208         {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 26 MHz   */
 209         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 210         {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}          /* 38.4 MHz */
 211 };
 212
 213 /* ABE M & N values with 32K clock as source */
 214 static const struct dpll_params abe_dpll_params_32k_196608khz = {
 215         750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
 216 };
 217
 218 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
 219 static const struct dpll_params
 220                 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
 221         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 12 MHz   */
 222         {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 223         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 16.8 MHz */
 224         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 19.2 MHz */
 225         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 226         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 227         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 228 };
 229
 230 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
 231         {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
 232         {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 20 MHz   */
 233         {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 16.8 MHz */
 234         {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 19.2 MHz */
 235         {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
 236         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 237         {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 38.4 MHz */
 238 };
 239
 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
 241         {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 12 MHz   */
 242         {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 20 MHz   */
 243         {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},          /* 16.8 MHz */
 244         {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 19.2 MHz */
 245         {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 26 MHz   */
 246         {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
 247         {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},         /* 38.4 MHz */
 248 };
 249
 250 struct dplls omap5_dplls_es1 = {
 251         .mpu = mpu_dpll_params_800mhz,
 252         .core = core_dpll_params_2128mhz_ddr532,
 253         .per = per_dpll_params_768mhz,
 254         .iva = iva_dpll_params_2330mhz,
 255 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 256         .abe = abe_dpll_params_sysclk_196608khz,
 257 #else
 258         .abe = &abe_dpll_params_32k_196608khz,
 259 #endif
 260         .usb = usb_dpll_params_1920mhz,
 261         .ddr = NULL
 262 };
 263
 264 struct dplls omap5_dplls_es2 = {
 265         .mpu = mpu_dpll_params_1100mhz,
 266         .core = core_dpll_params_2128mhz_ddr532_es2,
 267         .per = per_dpll_params_768mhz_es2,
 268         .iva = iva_dpll_params_2330mhz,
 269 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
 270         .abe = abe_dpll_params_sysclk_196608khz,
 271 #else
 272         .abe = &abe_dpll_params_32k_196608khz,
 273 #endif
 274         .usb = usb_dpll_params_1920mhz,
 275         .ddr = NULL
 276 };
 277
 278 struct dplls dra7xx_dplls = {
 279         .mpu = mpu_dpll_params_1ghz,
 280         .core = core_dpll_params_2128mhz_dra7xx,
 281         .per = per_dpll_params_768mhz_dra7xx,
 282         .abe = abe_dpll_params_sysclk2_361267khz,
 283         .iva = iva_dpll_params_2330mhz_dra7xx,
 284         .usb = usb_dpll_params_1920mhz,
 285         .ddr = ddr_dpll_params_2128mhz,
 286 };
 287
 288 struct pmic_data palmas = {
 289         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 290         .step = 10000, /* 10 mV represented in uV */
 291         /*
 292          * Offset codes 1-6 all give the base voltage in Palmas
 293          * Offset code 0 switches OFF the SMPS
 294          */
 295         .start_code = 6,
 296         .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
 297         .pmic_bus_init  = sri2c_init,
 298         .pmic_write     = omap_vc_bypass_send_value,
 299 };
 300
 301 struct pmic_data tps659038 = {
 302         .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
 303         .step = 10000, /* 10 mV represented in uV */
 304         /*
 305          * Offset codes 1-6 all give the base voltage in Palmas
 306          * Offset code 0 switches OFF the SMPS
 307          */
 308         .start_code = 6,
 309         .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
 310         .pmic_bus_init  = gpi2c_init,
 311         .pmic_write     = palmas_i2c_write_u8,
 312 };
 313
 314 struct vcores_data omap5430_volts = {
 315         .mpu.value = VDD_MPU,
 316         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 317         .mpu.pmic = &palmas,
 318
 319         .core.value = VDD_CORE,
 320         .core.addr = SMPS_REG_ADDR_8_CORE,
 321         .core.pmic = &palmas,
 322
 323         .mm.value = VDD_MM,
 324         .mm.addr = SMPS_REG_ADDR_45_IVA,
 325         .mm.pmic = &palmas,
 326 };
 327
 328 struct vcores_data omap5430_volts_es2 = {
 329         .mpu.value = VDD_MPU_ES2,
 330         .mpu.addr = SMPS_REG_ADDR_12_MPU,
 331         .mpu.pmic = &palmas,
 332
 333         .core.value = VDD_CORE_ES2,
 334         .core.addr = SMPS_REG_ADDR_8_CORE,
 335         .core.pmic = &palmas,
 336
 337         .mm.value = VDD_MM_ES2,
 338         .mm.addr = SMPS_REG_ADDR_45_IVA,
 339         .mm.pmic = &palmas,
 340 };
 341
 342 struct vcores_data dra752_volts = {
 343         .mpu.value      = VDD_MPU_DRA752,
 344         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
 345         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 346         .mpu.addr       = TPS659038_REG_ADDR_SMPS12_MPU,
 347         .mpu.pmic       = &tps659038,
 348
 349         .eve.value      = VDD_EVE_DRA752,
 350         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 351         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 352         .eve.addr       = TPS659038_REG_ADDR_SMPS45_EVE,
 353         .eve.pmic       = &tps659038,
 354
 355         .gpu.value      = VDD_GPU_DRA752,
 356         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
 357         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 358         .gpu.addr       = TPS659038_REG_ADDR_SMPS6_GPU,
 359         .gpu.pmic       = &tps659038,
 360
 361         .core.value     = VDD_CORE_DRA752,
 362         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
 363         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 364         .core.addr      = TPS659038_REG_ADDR_SMPS7_CORE,
 365         .core.pmic      = &tps659038,
 366
 367         .iva.value      = VDD_IVA_DRA752,
 368         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
 369         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 370         .iva.addr       = TPS659038_REG_ADDR_SMPS8_IVA,
 371         .iva.pmic       = &tps659038,
 372 };
 373
 374 /*
 375  * Enable essential clock domains, modules and
 376  * do some additional special settings needed
 377  */
 378 void enable_basic_clocks(void)
 379 {
 380         u32 const clk_domains_essential[] = {
 381                 (*prcm)->cm_l4per_clkstctrl,
 382                 (*prcm)->cm_l3init_clkstctrl,
 383                 (*prcm)->cm_memif_clkstctrl,
 384                 (*prcm)->cm_l4cfg_clkstctrl,
 385                 0
 386         };
 387
 388         u32 const clk_modules_hw_auto_essential[] = {
 389                 (*prcm)->cm_l3_gpmc_clkctrl,
 390                 (*prcm)->cm_memif_emif_1_clkctrl,
 391                 (*prcm)->cm_memif_emif_2_clkctrl,
 392                 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
 393                 (*prcm)->cm_wkup_gpio1_clkctrl,
 394                 (*prcm)->cm_l4per_gpio2_clkctrl,
 395                 (*prcm)->cm_l4per_gpio3_clkctrl,
 396                 (*prcm)->cm_l4per_gpio4_clkctrl,
 397                 (*prcm)->cm_l4per_gpio5_clkctrl,
 398                 (*prcm)->cm_l4per_gpio6_clkctrl,
 399                 (*prcm)->cm_l4per_gpio7_clkctrl,
 400                 (*prcm)->cm_l4per_gpio8_clkctrl,
 401                 0
 402         };
 403
 404         u32 const clk_modules_explicit_en_essential[] = {
 405                 (*prcm)->cm_wkup_gptimer1_clkctrl,
 406                 (*prcm)->cm_l3init_hsmmc1_clkctrl,
 407                 (*prcm)->cm_l3init_hsmmc2_clkctrl,
 408                 (*prcm)->cm_l4per_gptimer2_clkctrl,
 409                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 410                 (*prcm)->cm_l4per_uart3_clkctrl,
 411                 (*prcm)->cm_l4per_i2c1_clkctrl,
 412                 0
 413         };
 414
 415         /* Enable optional additional functional clock for GPIO4 */
 416         setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 417                         GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 418
 419         /* Enable 96 MHz clock for MMC1 & MMC2 */
 420         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 421                         HSMMC_CLKCTRL_CLKSEL_MASK);
 422         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 423                         HSMMC_CLKCTRL_CLKSEL_MASK);
 424
 425         /* Set the correct clock dividers for mmc */
 426         setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 427                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 428         setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 429                         HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 430
 431         /* Select 32KHz clock as the source of GPTIMER1 */
 432         setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
 433                         GPTIMER1_CLKCTRL_CLKSEL_MASK);
 434
 435         do_enable_clocks(clk_domains_essential,
 436                          clk_modules_hw_auto_essential,
 437                          clk_modules_explicit_en_essential,
 438                          1);
 439
 440         /* Enable SCRM OPT clocks for PER and CORE dpll */
 441         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 442                         OPTFCLKEN_SCRM_PER_MASK);
 443         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 444                         OPTFCLKEN_SCRM_CORE_MASK);
 445 }
 446
 447 void enable_basic_uboot_clocks(void)
 448 {
 449         u32 const clk_domains_essential[] = {
 450                 0
 451         };
 452
 453         u32 const clk_modules_hw_auto_essential[] = {
 454                 (*prcm)->cm_l3init_hsusbtll_clkctrl,
 455                 0
 456         };
 457
 458         u32 const clk_modules_explicit_en_essential[] = {
 459                 (*prcm)->cm_l4per_mcspi1_clkctrl,
 460                 (*prcm)->cm_l4per_i2c2_clkctrl,
 461                 (*prcm)->cm_l4per_i2c3_clkctrl,
 462                 (*prcm)->cm_l4per_i2c4_clkctrl,
 463                 (*prcm)->cm_l4per_i2c5_clkctrl,
 464                 (*prcm)->cm_l3init_hsusbhost_clkctrl,
 465                 (*prcm)->cm_l3init_fsusb_clkctrl,
 466                 0
 467         };
 468
 469         do_enable_clocks(clk_domains_essential,
 470                          clk_modules_hw_auto_essential,
 471                          clk_modules_explicit_en_essential,
 472                          1);
 473 }
 474
 475 /*
 476  * Enable non-essential clock domains, modules and
 477  * do some additional special settings needed
 478  */
 479 void enable_non_essential_clocks(void)
 480 {
 481         u32 const clk_domains_non_essential[] = {
 482                 (*prcm)->cm_mpu_m3_clkstctrl,
 483                 (*prcm)->cm_ivahd_clkstctrl,
 484                 (*prcm)->cm_dsp_clkstctrl,
 485                 (*prcm)->cm_dss_clkstctrl,
 486                 (*prcm)->cm_sgx_clkstctrl,
 487                 (*prcm)->cm1_abe_clkstctrl,
 488                 (*prcm)->cm_c2c_clkstctrl,
 489                 (*prcm)->cm_cam_clkstctrl,
 490                 (*prcm)->cm_dss_clkstctrl,
 491                 (*prcm)->cm_sdma_clkstctrl,
 492                 0
 493         };
 494
 495         u32 const clk_modules_hw_auto_non_essential[] = {
 496                 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
 497                 (*prcm)->cm_ivahd_ivahd_clkctrl,
 498                 (*prcm)->cm_ivahd_sl2_clkctrl,
 499                 (*prcm)->cm_dsp_dsp_clkctrl,
 500                 (*prcm)->cm_l3instr_l3_3_clkctrl,
 501                 (*prcm)->cm_l3instr_l3_instr_clkctrl,
 502                 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
 503                 (*prcm)->cm_l3init_hsi_clkctrl,
 504                 (*prcm)->cm_l4per_hdq1w_clkctrl,
 505                 0
 506         };
 507
 508         u32 const clk_modules_explicit_en_non_essential[] = {
 509                 (*prcm)->cm1_abe_aess_clkctrl,
 510                 (*prcm)->cm1_abe_pdm_clkctrl,
 511                 (*prcm)->cm1_abe_dmic_clkctrl,
 512                 (*prcm)->cm1_abe_mcasp_clkctrl,
 513                 (*prcm)->cm1_abe_mcbsp1_clkctrl,
 514                 (*prcm)->cm1_abe_mcbsp2_clkctrl,
 515                 (*prcm)->cm1_abe_mcbsp3_clkctrl,
 516                 (*prcm)->cm1_abe_slimbus_clkctrl,
 517                 (*prcm)->cm1_abe_timer5_clkctrl,
 518                 (*prcm)->cm1_abe_timer6_clkctrl,
 519                 (*prcm)->cm1_abe_timer7_clkctrl,
 520                 (*prcm)->cm1_abe_timer8_clkctrl,
 521                 (*prcm)->cm1_abe_wdt3_clkctrl,
 522                 (*prcm)->cm_l4per_gptimer9_clkctrl,
 523                 (*prcm)->cm_l4per_gptimer10_clkctrl,
 524                 (*prcm)->cm_l4per_gptimer11_clkctrl,
 525                 (*prcm)->cm_l4per_gptimer3_clkctrl,
 526                 (*prcm)->cm_l4per_gptimer4_clkctrl,
 527                 (*prcm)->cm_l4per_mcspi2_clkctrl,
 528                 (*prcm)->cm_l4per_mcspi3_clkctrl,
 529                 (*prcm)->cm_l4per_mcspi4_clkctrl,
 530                 (*prcm)->cm_l4per_mmcsd3_clkctrl,
 531                 (*prcm)->cm_l4per_mmcsd4_clkctrl,
 532                 (*prcm)->cm_l4per_mmcsd5_clkctrl,
 533                 (*prcm)->cm_l4per_uart1_clkctrl,
 534                 (*prcm)->cm_l4per_uart2_clkctrl,
 535                 (*prcm)->cm_l4per_uart4_clkctrl,
 536                 (*prcm)->cm_wkup_keyboard_clkctrl,
 537                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
 538                 (*prcm)->cm_cam_iss_clkctrl,
 539                 (*prcm)->cm_cam_fdif_clkctrl,
 540                 (*prcm)->cm_dss_dss_clkctrl,
 541                 (*prcm)->cm_sgx_sgx_clkctrl,
 542                 0
 543         };
 544
 545         /* Enable optional functional clock for ISS */
 546         setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
 547
 548         /* Enable all optional functional clocks of DSS */
 549         setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
 550
 551         do_enable_clocks(clk_domains_non_essential,
 552                          clk_modules_hw_auto_non_essential,
 553                          clk_modules_explicit_en_non_essential,
 554                          0);
 555
 556         /* Put camera module in no sleep mode */
 557         clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
 558                         MODULE_CLKCTRL_MODULEMODE_MASK,
 559                         CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
 560                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 561 }
 562
 563 const struct ctrl_ioregs ioregs_omap5430 = {
 564         .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 565         .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
 566         .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
 567         .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
 568         .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
 569 };
 570
 571 const struct ctrl_ioregs ioregs_omap5432_es1 = {
 572         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 573         .ctrl_lpddr2ch = 0x0,
 574         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
 575         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 576         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 577         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 578         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 579 };
 580
 581 const struct ctrl_ioregs ioregs_omap5432_es2 = {
 582         .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 583         .ctrl_lpddr2ch = 0x0,
 584         .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
 585         .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
 586         .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 587         .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 588         .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 589 };
 590
 591 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 592         .ctrl_ddrch = 0x40404040,
 593         .ctrl_lpddr2ch = 0x40404040,
 594         .ctrl_ddr3ch = 0x80808080,
 595         .ctrl_ddrio_0 = 0xbae8c631,
 596         .ctrl_ddrio_1 = 0xb46318d8,
 597         .ctrl_ddrio_2 = 0x84210000,
 598         .ctrl_emif_sdram_config_ext = 0xb2c00000,
 599         .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 600 };
 601
 602 void hw_data_init(void)
 603 {
 604         u32 omap_rev = omap_revision();
 605
 606         switch (omap_rev) {
 607
 608         case OMAP5430_ES1_0:
 609         case OMAP5432_ES1_0:
 610         *prcm = &omap5_es1_prcm;
 611         *dplls_data = &omap5_dplls_es1;
 612         *omap_vcores = &omap5430_volts;
 613         *ctrl = &omap5_ctrl;
 614         break;
 615
 616         case OMAP5430_ES2_0:
 617         case OMAP5432_ES2_0:
 618         *prcm = &omap5_es2_prcm;
 619         *dplls_data = &omap5_dplls_es2;
 620         *omap_vcores = &omap5430_volts_es2;
 621         *ctrl = &omap5_ctrl;
 622         break;
 623
 624         case DRA752_ES1_0:
 625         *prcm = &dra7xx_prcm;
 626         *dplls_data = &dra7xx_dplls;
 627         *omap_vcores = &dra752_volts;
 628         *ctrl = &dra7xx_ctrl;
 629         break;
 630
 631         default:
 632                 printf("\n INVALID OMAP REVISION ");
 633         }
 634 }
 635
 636 void get_ioregs(const struct ctrl_ioregs **regs)
 637 {
 638         u32 omap_rev = omap_revision();
 639
 640         switch (omap_rev) {
 641         case OMAP5430_ES1_0:
 642         case OMAP5430_ES2_0:
 643                 *regs = &ioregs_omap5430;
 644                 break;
 645         case OMAP5432_ES1_0:
 646                 *regs = &ioregs_omap5432_es1;
 647                 break;
 648         case OMAP5432_ES2_0:
 649                 *regs = &ioregs_omap5432_es2;
 650                 break;
 651         case DRA752_ES1_0:
 652                 *regs = &ioregs_dra7xx_es1;
 653                 break;
 654
 655         default:
 656                 printf("\n INVALID OMAP REVISION ");
 657         }
 658 }