arch/arm/cpu/armv7/omap5/prcm-regs.c

   1 /*
   2  *
   3  * HW regs data for OMAP5 Soc
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Sricharan R <r.sricharan@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <asm/omap_common.h>
  30
  31 struct prcm_regs const omap5_es1_prcm = {
  32         /* cm1.ckgen */
  33         .cm_clksel_core = 0x4a004100,
  34         .cm_clksel_abe = 0x4a004108,
  35         .cm_dll_ctrl = 0x4a004110,
  36         .cm_clkmode_dpll_core = 0x4a004120,
  37         .cm_idlest_dpll_core = 0x4a004124,
  38         .cm_autoidle_dpll_core = 0x4a004128,
  39         .cm_clksel_dpll_core = 0x4a00412c,
  40         .cm_div_m2_dpll_core = 0x4a004130,
  41         .cm_div_m3_dpll_core = 0x4a004134,
  42         .cm_div_h11_dpll_core = 0x4a004138,
  43         .cm_div_h12_dpll_core = 0x4a00413c,
  44         .cm_div_h13_dpll_core = 0x4a004140,
  45         .cm_div_h14_dpll_core = 0x4a004144,
  46         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
  47         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
  48         .cm_emu_override_dpll_core = 0x4a004150,
  49         .cm_div_h22_dpllcore = 0x4a004154,
  50         .cm_div_h23_dpll_core = 0x4a004158,
  51         .cm_clkmode_dpll_mpu = 0x4a004160,
  52         .cm_idlest_dpll_mpu = 0x4a004164,
  53         .cm_autoidle_dpll_mpu = 0x4a004168,
  54         .cm_clksel_dpll_mpu = 0x4a00416c,
  55         .cm_div_m2_dpll_mpu = 0x4a004170,
  56         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
  57         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
  58         .cm_bypclk_dpll_mpu = 0x4a00419c,
  59         .cm_clkmode_dpll_iva = 0x4a0041a0,
  60         .cm_idlest_dpll_iva = 0x4a0041a4,
  61         .cm_autoidle_dpll_iva = 0x4a0041a8,
  62         .cm_clksel_dpll_iva = 0x4a0041ac,
  63         .cm_div_h11_dpll_iva = 0x4a0041b8,
  64         .cm_div_h12_dpll_iva = 0x4a0041bc,
  65         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
  66         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
  67         .cm_bypclk_dpll_iva = 0x4a0041dc,
  68         .cm_clkmode_dpll_abe = 0x4a0041e0,
  69         .cm_idlest_dpll_abe = 0x4a0041e4,
  70         .cm_autoidle_dpll_abe = 0x4a0041e8,
  71         .cm_clksel_dpll_abe = 0x4a0041ec,
  72         .cm_div_m2_dpll_abe = 0x4a0041f0,
  73         .cm_div_m3_dpll_abe = 0x4a0041f4,
  74         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
  75         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
  76         .cm_clkmode_dpll_ddrphy = 0x4a004220,
  77         .cm_idlest_dpll_ddrphy = 0x4a004224,
  78         .cm_autoidle_dpll_ddrphy = 0x4a004228,
  79         .cm_clksel_dpll_ddrphy = 0x4a00422c,
  80         .cm_div_m2_dpll_ddrphy = 0x4a004230,
  81         .cm_div_h11_dpll_ddrphy = 0x4a004238,
  82         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
  83         .cm_div_h13_dpll_ddrphy = 0x4a004240,
  84         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
  85         .cm_shadow_freq_config1 = 0x4a004260,
  86         .cm_mpu_mpu_clkctrl = 0x4a004320,
  87
  88         /* cm1.dsp */
  89         .cm_dsp_clkstctrl = 0x4a004400,
  90         .cm_dsp_dsp_clkctrl = 0x4a004420,
  91
  92         /* cm1.abe */
  93         .cm1_abe_clkstctrl = 0x4a004500,
  94         .cm1_abe_l4abe_clkctrl = 0x4a004520,
  95         .cm1_abe_aess_clkctrl = 0x4a004528,
  96         .cm1_abe_pdm_clkctrl = 0x4a004530,
  97         .cm1_abe_dmic_clkctrl = 0x4a004538,
  98         .cm1_abe_mcasp_clkctrl = 0x4a004540,
  99         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
 100         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
 101         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
 102         .cm1_abe_slimbus_clkctrl = 0x4a004560,
 103         .cm1_abe_timer5_clkctrl = 0x4a004568,
 104         .cm1_abe_timer6_clkctrl = 0x4a004570,
 105         .cm1_abe_timer7_clkctrl = 0x4a004578,
 106         .cm1_abe_timer8_clkctrl = 0x4a004580,
 107         .cm1_abe_wdt3_clkctrl = 0x4a004588,
 108
 109         /* cm2.ckgen */
 110         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
 111         .cm_clksel_usb_60mhz = 0x4a008104,
 112         .cm_scale_fclk = 0x4a008108,
 113         .cm_core_dvfs_perf1 = 0x4a008110,
 114         .cm_core_dvfs_perf2 = 0x4a008114,
 115         .cm_core_dvfs_perf3 = 0x4a008118,
 116         .cm_core_dvfs_perf4 = 0x4a00811c,
 117         .cm_core_dvfs_current = 0x4a008124,
 118         .cm_iva_dvfs_perf_tesla = 0x4a008128,
 119         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
 120         .cm_iva_dvfs_perf_abe = 0x4a008130,
 121         .cm_iva_dvfs_current = 0x4a008138,
 122         .cm_clkmode_dpll_per = 0x4a008140,
 123         .cm_idlest_dpll_per = 0x4a008144,
 124         .cm_autoidle_dpll_per = 0x4a008148,
 125         .cm_clksel_dpll_per = 0x4a00814c,
 126         .cm_div_m2_dpll_per = 0x4a008150,
 127         .cm_div_m3_dpll_per = 0x4a008154,
 128         .cm_div_h11_dpll_per = 0x4a008158,
 129         .cm_div_h12_dpll_per = 0x4a00815c,
 130         .cm_div_h14_dpll_per = 0x4a008164,
 131         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
 132         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
 133         .cm_emu_override_dpll_per = 0x4a008170,
 134         .cm_clkmode_dpll_usb = 0x4a008180,
 135         .cm_idlest_dpll_usb = 0x4a008184,
 136         .cm_autoidle_dpll_usb = 0x4a008188,
 137         .cm_clksel_dpll_usb = 0x4a00818c,
 138         .cm_div_m2_dpll_usb = 0x4a008190,
 139         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
 140         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
 141         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
 142         .cm_clkmode_dpll_unipro = 0x4a0081c0,
 143         .cm_idlest_dpll_unipro = 0x4a0081c4,
 144         .cm_autoidle_dpll_unipro = 0x4a0081c8,
 145         .cm_clksel_dpll_unipro = 0x4a0081cc,
 146         .cm_div_m2_dpll_unipro = 0x4a0081d0,
 147         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
 148         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
 149
 150         /* cm2.core */
 151         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
 152         .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
 153         .cm_l3_1_clkstctrl = 0x4a008700,
 154         .cm_l3_1_dynamicdep = 0x4a008708,
 155         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
 156         .cm_l3_2_clkstctrl = 0x4a008800,
 157         .cm_l3_2_dynamicdep = 0x4a008808,
 158         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
 159         .cm_l3_gpmc_clkctrl = 0x4a008828,
 160         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
 161         .cm_mpu_m3_clkstctrl = 0x4a008900,
 162         .cm_mpu_m3_staticdep = 0x4a008904,
 163         .cm_mpu_m3_dynamicdep = 0x4a008908,
 164         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
 165         .cm_sdma_clkstctrl = 0x4a008a00,
 166         .cm_sdma_staticdep = 0x4a008a04,
 167         .cm_sdma_dynamicdep = 0x4a008a08,
 168         .cm_sdma_sdma_clkctrl = 0x4a008a20,
 169         .cm_memif_clkstctrl = 0x4a008b00,
 170         .cm_memif_dmm_clkctrl = 0x4a008b20,
 171         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
 172         .cm_memif_emif_1_clkctrl = 0x4a008b30,
 173         .cm_memif_emif_2_clkctrl = 0x4a008b38,
 174         .cm_memif_dll_clkctrl = 0x4a008b40,
 175         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
 176         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
 177         .cm_memif_dll_h_clkctrl = 0x4a008b60,
 178         .cm_c2c_clkstctrl = 0x4a008c00,
 179         .cm_c2c_staticdep = 0x4a008c04,
 180         .cm_c2c_dynamicdep = 0x4a008c08,
 181         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
 182         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
 183         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
 184         .cm_l4cfg_clkstctrl = 0x4a008d00,
 185         .cm_l4cfg_dynamicdep = 0x4a008d08,
 186         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
 187         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
 188         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
 189         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
 190         .cm_l3instr_clkstctrl = 0x4a008e00,
 191         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
 192         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
 193         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
 194
 195         /* cm2.ivahd */
 196         .cm_ivahd_clkstctrl = 0x4a008f00,
 197         .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
 198         .cm_ivahd_sl2_clkctrl = 0x4a008f28,
 199
 200         /* cm2.cam */
 201         .cm_cam_clkstctrl = 0x4a009000,
 202         .cm_cam_iss_clkctrl = 0x4a009020,
 203         .cm_cam_fdif_clkctrl = 0x4a009028,
 204
 205         /* cm2.dss */
 206         .cm_dss_clkstctrl = 0x4a009100,
 207         .cm_dss_dss_clkctrl = 0x4a009120,
 208
 209         /* cm2.sgx */
 210         .cm_sgx_clkstctrl = 0x4a009200,
 211         .cm_sgx_sgx_clkctrl = 0x4a009220,
 212
 213         /* cm2.l3init */
 214         .cm_l3init_clkstctrl = 0x4a009300,
 215         .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
 216         .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
 217         .cm_l3init_hsi_clkctrl = 0x4a009338,
 218         .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
 219         .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
 220         .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
 221         .cm_l3init_p1500_clkctrl = 0x4a009378,
 222         .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
 223         .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
 224
 225         /* cm2.l4per */
 226         .cm_l4per_clkstctrl = 0x4a009400,
 227         .cm_l4per_dynamicdep = 0x4a009408,
 228         .cm_l4per_adc_clkctrl = 0x4a009420,
 229         .cm_l4per_gptimer10_clkctrl = 0x4a009428,
 230         .cm_l4per_gptimer11_clkctrl = 0x4a009430,
 231         .cm_l4per_gptimer2_clkctrl = 0x4a009438,
 232         .cm_l4per_gptimer3_clkctrl = 0x4a009440,
 233         .cm_l4per_gptimer4_clkctrl = 0x4a009448,
 234         .cm_l4per_gptimer9_clkctrl = 0x4a009450,
 235         .cm_l4per_elm_clkctrl = 0x4a009458,
 236         .cm_l4per_gpio2_clkctrl = 0x4a009460,
 237         .cm_l4per_gpio3_clkctrl = 0x4a009468,
 238         .cm_l4per_gpio4_clkctrl = 0x4a009470,
 239         .cm_l4per_gpio5_clkctrl = 0x4a009478,
 240         .cm_l4per_gpio6_clkctrl = 0x4a009480,
 241         .cm_l4per_hdq1w_clkctrl = 0x4a009488,
 242         .cm_l4per_hecc1_clkctrl = 0x4a009490,
 243         .cm_l4per_hecc2_clkctrl = 0x4a009498,
 244         .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
 245         .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
 246         .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
 247         .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
 248         .cm_l4per_l4per_clkctrl = 0x4a0094c0,
 249         .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
 250         .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
 251         .cm_l4per_mgate_clkctrl = 0x4a0094e8,
 252         .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
 253         .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
 254         .cm_l4per_mcspi3_clkctrl = 0x4a009500,
 255         .cm_l4per_mcspi4_clkctrl = 0x4a009508,
 256         .cm_l4per_gpio7_clkctrl = 0x4a009510,
 257         .cm_l4per_gpio8_clkctrl = 0x4a009518,
 258         .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
 259         .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
 260         .cm_l4per_msprohg_clkctrl = 0x4a009530,
 261         .cm_l4per_slimbus2_clkctrl = 0x4a009538,
 262         .cm_l4per_uart1_clkctrl = 0x4a009540,
 263         .cm_l4per_uart2_clkctrl = 0x4a009548,
 264         .cm_l4per_uart3_clkctrl = 0x4a009550,
 265         .cm_l4per_uart4_clkctrl = 0x4a009558,
 266         .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
 267         .cm_l4per_i2c5_clkctrl = 0x4a009568,
 268         .cm_l4per_uart5_clkctrl = 0x4a009570,
 269         .cm_l4per_uart6_clkctrl = 0x4a009578,
 270         .cm_l4sec_clkstctrl = 0x4a009580,
 271         .cm_l4sec_staticdep = 0x4a009584,
 272         .cm_l4sec_dynamicdep = 0x4a009588,
 273         .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
 274         .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
 275         .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
 276         .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
 277         .cm_l4sec_rng_clkctrl = 0x4a0095c0,
 278         .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
 279         .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
 280
 281         /* l4 wkup regs */
 282         .cm_abe_pll_ref_clksel = 0x4ae0610c,
 283         .cm_sys_clksel = 0x4ae06110,
 284         .cm_wkup_clkstctrl = 0x4ae07800,
 285         .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
 286         .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
 287         .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
 288         .cm_wkup_gpio1_clkctrl = 0x4ae07838,
 289         .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
 290         .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
 291         .cm_wkup_synctimer_clkctrl = 0x4ae07850,
 292         .cm_wkup_usim_clkctrl = 0x4ae07858,
 293         .cm_wkup_sarram_clkctrl = 0x4ae07860,
 294         .cm_wkup_keyboard_clkctrl = 0x4ae07878,
 295         .cm_wkup_rtc_clkctrl = 0x4ae07880,
 296         .cm_wkup_bandgap_clkctrl = 0x4ae07888,
 297         .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
 298         .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
 299         .prm_rstctrl = 0x4ae07b00,
 300         .prm_rstst = 0x4ae07b04,
 301         .prm_rsttime = 0x4ae07b08,
 302         .prm_vc_val_bypass = 0x4ae07ba0,
 303         .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
 304         .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
 305         .prm_sldo_core_setup = 0x4ae07bc4,
 306         .prm_sldo_core_ctrl = 0x4ae07bc8,
 307         .prm_sldo_mpu_setup = 0x4ae07bcc,
 308         .prm_sldo_mpu_ctrl = 0x4ae07bd0,
 309         .prm_sldo_mm_setup = 0x4ae07bd4,
 310         .prm_sldo_mm_ctrl = 0x4ae07bd8,
 311 };
 312
 313 struct omap_sys_ctrl_regs const omap5_ctrl = {
 314         .control_status                         = 0x4A002134,
 315         .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
 316         .control_padconf_core_base              = 0x4A002800,
 317         .control_paconf_global                  = 0x4A002DA0,
 318         .control_paconf_mode                    = 0x4A002DA4,
 319         .control_smart1io_padconf_0             = 0x4A002DA8,
 320         .control_smart1io_padconf_1             = 0x4A002DAC,
 321         .control_smart1io_padconf_2             = 0x4A002DB0,
 322         .control_smart2io_padconf_0             = 0x4A002DB4,
 323         .control_smart2io_padconf_1             = 0x4A002DB8,
 324         .control_smart2io_padconf_2             = 0x4A002DBC,
 325         .control_smart3io_padconf_0             = 0x4A002DC0,
 326         .control_smart3io_padconf_1             = 0x4A002DC4,
 327         .control_pbias                          = 0x4A002E00,
 328         .control_i2c_0                          = 0x4A002E04,
 329         .control_camera_rx                      = 0x4A002E08,
 330         .control_hdmi_tx_phy                    = 0x4A002E0C,
 331         .control_uniportm                       = 0x4A002E10,
 332         .control_dsiphy                         = 0x4A002E14,
 333         .control_mcbsplp                        = 0x4A002E18,
 334         .control_usb2phycore                    = 0x4A002E1C,
 335         .control_hdmi_1                         = 0x4A002E20,
 336         .control_hsi                            = 0x4A002E24,
 337         .control_ddr3ch1_0                      = 0x4A002E30,
 338         .control_ddr3ch2_0                      = 0x4A002E34,
 339         .control_ddrch1_0                       = 0x4A002E38,
 340         .control_ddrch1_1                       = 0x4A002E3C,
 341         .control_ddrch2_0                       = 0x4A002E40,
 342         .control_ddrch2_1                       = 0x4A002E44,
 343         .control_lpddr2ch1_0                    = 0x4A002E48,
 344         .control_lpddr2ch1_1                    = 0x4A002E4C,
 345         .control_ddrio_0                        = 0x4A002E50,
 346         .control_ddrio_1                        = 0x4A002E54,
 347         .control_ddrio_2                        = 0x4A002E58,
 348         .control_hyst_1                         = 0x4A002E5C,
 349         .control_usbb_hsic_control              = 0x4A002E60,
 350         .control_c2c                            = 0x4A002E64,
 351         .control_core_control_spare_rw          = 0x4A002E68,
 352         .control_core_control_spare_r           = 0x4A002E6C,
 353         .control_core_control_spare_r_c0        = 0x4A002E70,
 354         .control_srcomp_north_side              = 0x4A002E74,
 355         .control_srcomp_south_side              = 0x4A002E78,
 356         .control_srcomp_east_side               = 0x4A002E7C,
 357         .control_srcomp_west_side               = 0x4A002E80,
 358         .control_srcomp_code_latch              = 0x4A002E84,
 359         .control_port_emif1_sdram_config        = 0x4AE0C110,
 360         .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
 361         .control_port_emif2_sdram_config        = 0x4AE0C118,
 362         .control_emif1_sdram_config_ext         = 0x4AE0C144,
 363         .control_emif2_sdram_config_ext         = 0x4AE0C148,
 364         .control_wkup_ldovbb_mpu_voltage_ctrl   = 0x4AE0C318,
 365         .control_padconf_wkup_base              = 0x4AE0C800,
 366         .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
 367         .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
 368         .control_padconf_mode                   = 0x4AE0CDA8,
 369         .control_xtal_oscillator                = 0x4AE0CDAC,
 370         .control_i2c_2                          = 0x4AE0CDB0,
 371         .control_ckobuffer                      = 0x4AE0CDB4,
 372         .control_wkup_control_spare_rw          = 0x4AE0CDB8,
 373         .control_wkup_control_spare_r           = 0x4AE0CDBC,
 374         .control_wkup_control_spare_r_c0        = 0x4AE0CDC0,
 375         .control_srcomp_east_side_wkup          = 0x4AE0CDC4,
 376         .control_efuse_1                        = 0x4AE0CDC8,
 377         .control_efuse_2                        = 0x4AE0CDCC,
 378         .control_efuse_3                        = 0x4AE0CDD0,
 379         .control_efuse_4                        = 0x4AE0CDD4,
 380         .control_efuse_5                        = 0x4AE0CDD8,
 381         .control_efuse_6                        = 0x4AE0CDDC,
 382         .control_efuse_7                        = 0x4AE0CDE0,
 383         .control_efuse_8                        = 0x4AE0CDE4,
 384         .control_efuse_9                        = 0x4AE0CDE8,
 385         .control_efuse_10                       = 0x4AE0CDEC,
 386         .control_efuse_11                       = 0x4AE0CDF0,
 387         .control_efuse_12                       = 0x4AE0CDF4,
 388         .control_efuse_13                       = 0x4AE0CDF8,
 389 };
 390
 391 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 392         .control_status                         = 0x4A002134,
 393         .control_core_mmr_lock1                 = 0x4A002540,
 394         .control_core_mmr_lock2                 = 0x4A002544,
 395         .control_core_mmr_lock3                 = 0x4A002548,
 396         .control_core_mmr_lock4                 = 0x4A00254C,
 397         .control_core_mmr_lock5                 = 0x4A002550,
 398         .control_core_control_io1               = 0x4A002554,
 399         .control_core_control_io2               = 0x4A002558,
 400         .control_paconf_global                  = 0x4A002DA0,
 401         .control_paconf_mode                    = 0x4A002DA4,
 402         .control_smart1io_padconf_0             = 0x4A002DA8,
 403         .control_smart1io_padconf_1             = 0x4A002DAC,
 404         .control_smart1io_padconf_2             = 0x4A002DB0,
 405         .control_smart2io_padconf_0             = 0x4A002DB4,
 406         .control_smart2io_padconf_1             = 0x4A002DB8,
 407         .control_smart2io_padconf_2             = 0x4A002DBC,
 408         .control_smart3io_padconf_0             = 0x4A002DC0,
 409         .control_smart3io_padconf_1             = 0x4A002DC4,
 410         .control_pbias                          = 0x4A002E00,
 411         .control_i2c_0                          = 0x4A002E04,
 412         .control_camera_rx                      = 0x4A002E08,
 413         .control_hdmi_tx_phy                    = 0x4A002E0C,
 414         .control_uniportm                       = 0x4A002E10,
 415         .control_dsiphy                         = 0x4A002E14,
 416         .control_mcbsplp                        = 0x4A002E18,
 417         .control_usb2phycore                    = 0x4A002E1C,
 418         .control_hdmi_1                         = 0x4A002E20,
 419         .control_hsi                            = 0x4A002E24,
 420         .control_ddr3ch1_0                      = 0x4A002E30,
 421         .control_ddr3ch2_0                      = 0x4A002E34,
 422         .control_ddrch1_0                       = 0x4A002E38,
 423         .control_ddrch1_1                       = 0x4A002E3C,
 424         .control_ddrch2_0                       = 0x4A002E40,
 425         .control_ddrch2_1                       = 0x4A002E44,
 426         .control_lpddr2ch1_0                    = 0x4A002E48,
 427         .control_lpddr2ch1_1                    = 0x4A002E4C,
 428         .control_ddrio_0                        = 0x4A002E50,
 429         .control_ddrio_1                        = 0x4A002E54,
 430         .control_ddrio_2                        = 0x4A002E58,
 431         .control_hyst_1                         = 0x4A002E5C,
 432         .control_usbb_hsic_control              = 0x4A002E60,
 433         .control_c2c                            = 0x4A002E64,
 434         .control_core_control_spare_rw          = 0x4A002E68,
 435         .control_core_control_spare_r           = 0x4A002E6C,
 436         .control_core_control_spare_r_c0        = 0x4A002E70,
 437         .control_srcomp_north_side              = 0x4A002E74,
 438         .control_srcomp_south_side              = 0x4A002E78,
 439         .control_srcomp_east_side               = 0x4A002E7C,
 440         .control_srcomp_west_side               = 0x4A002E80,
 441         .control_srcomp_code_latch              = 0x4A002E84,
 442         .control_ddr_control_ext_0              = 0x4A002E88,
 443         .control_padconf_core_base              = 0x4A003400,
 444         .control_port_emif1_sdram_config        = 0x4AE0C110,
 445         .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
 446         .control_port_emif2_sdram_config        = 0x4AE0C118,
 447         .control_emif1_sdram_config_ext         = 0x4AE0C144,
 448         .control_emif2_sdram_config_ext         = 0x4AE0C148,
 449         .control_padconf_mode                   = 0x4AE0C5A0,
 450         .control_xtal_oscillator                = 0x4AE0C5A4,
 451         .control_i2c_2                          = 0x4AE0C5A8,
 452         .control_ckobuffer                      = 0x4AE0C5AC,
 453         .control_wkup_control_spare_rw          = 0x4AE0C5B0,
 454         .control_wkup_control_spare_r           = 0x4AE0C5B4,
 455         .control_wkup_control_spare_r_c0        = 0x4AE0C5B8,
 456         .control_srcomp_east_side_wkup          = 0x4AE0C5BC,
 457         .control_efuse_1                        = 0x4AE0C5C0,
 458         .control_efuse_2                        = 0x4AE0C5C4,
 459         .control_efuse_3                        = 0x4AE0C5C8,
 460         .control_efuse_4                        = 0x4AE0C5CC,
 461         .control_efuse_13                       = 0x4AE0C5F0,
 462 };
 463
 464 struct prcm_regs const omap5_es2_prcm = {
 465         /* cm1.ckgen */
 466         .cm_clksel_core = 0x4a004100,
 467         .cm_clksel_abe = 0x4a004108,
 468         .cm_dll_ctrl = 0x4a004110,
 469         .cm_clkmode_dpll_core = 0x4a004120,
 470         .cm_idlest_dpll_core = 0x4a004124,
 471         .cm_autoidle_dpll_core = 0x4a004128,
 472         .cm_clksel_dpll_core = 0x4a00412c,
 473         .cm_div_m2_dpll_core = 0x4a004130,
 474         .cm_div_m3_dpll_core = 0x4a004134,
 475         .cm_div_h11_dpll_core = 0x4a004138,
 476         .cm_div_h12_dpll_core = 0x4a00413c,
 477         .cm_div_h13_dpll_core = 0x4a004140,
 478         .cm_div_h14_dpll_core = 0x4a004144,
 479         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
 480         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
 481         .cm_div_h21_dpll_core = 0x4a004150,
 482         .cm_div_h22_dpllcore = 0x4a004154,
 483         .cm_div_h23_dpll_core = 0x4a004158,
 484         .cm_div_h24_dpll_core = 0x4a00415c,
 485         .cm_clkmode_dpll_mpu = 0x4a004160,
 486         .cm_idlest_dpll_mpu = 0x4a004164,
 487         .cm_autoidle_dpll_mpu = 0x4a004168,
 488         .cm_clksel_dpll_mpu = 0x4a00416c,
 489         .cm_div_m2_dpll_mpu = 0x4a004170,
 490         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
 491         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
 492         .cm_bypclk_dpll_mpu = 0x4a00419c,
 493         .cm_clkmode_dpll_iva = 0x4a0041a0,
 494         .cm_idlest_dpll_iva = 0x4a0041a4,
 495         .cm_autoidle_dpll_iva = 0x4a0041a8,
 496         .cm_clksel_dpll_iva = 0x4a0041ac,
 497         .cm_div_h11_dpll_iva = 0x4a0041b8,
 498         .cm_div_h12_dpll_iva = 0x4a0041bc,
 499         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
 500         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
 501         .cm_bypclk_dpll_iva = 0x4a0041dc,
 502         .cm_clkmode_dpll_abe = 0x4a0041e0,
 503         .cm_idlest_dpll_abe = 0x4a0041e4,
 504         .cm_autoidle_dpll_abe = 0x4a0041e8,
 505         .cm_clksel_dpll_abe = 0x4a0041ec,
 506         .cm_div_m2_dpll_abe = 0x4a0041f0,
 507         .cm_div_m3_dpll_abe = 0x4a0041f4,
 508         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
 509         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
 510         .cm_clkmode_dpll_ddrphy = 0x4a004220,
 511         .cm_idlest_dpll_ddrphy = 0x4a004224,
 512         .cm_autoidle_dpll_ddrphy = 0x4a004228,
 513         .cm_clksel_dpll_ddrphy = 0x4a00422c,
 514         .cm_div_m2_dpll_ddrphy = 0x4a004230,
 515         .cm_div_h11_dpll_ddrphy = 0x4a004238,
 516         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
 517         .cm_div_h13_dpll_ddrphy = 0x4a004240,
 518         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
 519         .cm_shadow_freq_config1 = 0x4a004260,
 520         .cm_mpu_mpu_clkctrl = 0x4a004320,
 521
 522         /* cm1.dsp */
 523         .cm_dsp_clkstctrl = 0x4a004400,
 524         .cm_dsp_dsp_clkctrl = 0x4a004420,
 525
 526         /* cm1.abe */
 527         .cm1_abe_clkstctrl = 0x4a004500,
 528         .cm1_abe_l4abe_clkctrl = 0x4a004520,
 529         .cm1_abe_aess_clkctrl = 0x4a004528,
 530         .cm1_abe_pdm_clkctrl = 0x4a004530,
 531         .cm1_abe_dmic_clkctrl = 0x4a004538,
 532         .cm1_abe_mcasp_clkctrl = 0x4a004540,
 533         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
 534         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
 535         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
 536         .cm1_abe_slimbus_clkctrl = 0x4a004560,
 537         .cm1_abe_timer5_clkctrl = 0x4a004568,
 538         .cm1_abe_timer6_clkctrl = 0x4a004570,
 539         .cm1_abe_timer7_clkctrl = 0x4a004578,
 540         .cm1_abe_timer8_clkctrl = 0x4a004580,
 541         .cm1_abe_wdt3_clkctrl = 0x4a004588,
 542
 543
 544
 545         /* cm2.ckgen */
 546         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
 547         .cm_clksel_usb_60mhz = 0x4a008104,
 548         .cm_scale_fclk = 0x4a008108,
 549         .cm_core_dvfs_perf1 = 0x4a008110,
 550         .cm_core_dvfs_perf2 = 0x4a008114,
 551         .cm_core_dvfs_perf3 = 0x4a008118,
 552         .cm_core_dvfs_perf4 = 0x4a00811c,
 553         .cm_core_dvfs_current = 0x4a008124,
 554         .cm_iva_dvfs_perf_tesla = 0x4a008128,
 555         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
 556         .cm_iva_dvfs_perf_abe = 0x4a008130,
 557         .cm_iva_dvfs_current = 0x4a008138,
 558         .cm_clkmode_dpll_per = 0x4a008140,
 559         .cm_idlest_dpll_per = 0x4a008144,
 560         .cm_autoidle_dpll_per = 0x4a008148,
 561         .cm_clksel_dpll_per = 0x4a00814c,
 562         .cm_div_m2_dpll_per = 0x4a008150,
 563         .cm_div_m3_dpll_per = 0x4a008154,
 564         .cm_div_h11_dpll_per = 0x4a008158,
 565         .cm_div_h12_dpll_per = 0x4a00815c,
 566         .cm_div_h13_dpll_per = 0x4a008160,
 567         .cm_div_h14_dpll_per = 0x4a008164,
 568         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
 569         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
 570         .cm_emu_override_dpll_per = 0x4a008170,
 571         .cm_clkmode_dpll_usb = 0x4a008180,
 572         .cm_idlest_dpll_usb = 0x4a008184,
 573         .cm_autoidle_dpll_usb = 0x4a008188,
 574         .cm_clksel_dpll_usb = 0x4a00818c,
 575         .cm_div_m2_dpll_usb = 0x4a008190,
 576         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
 577         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
 578         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
 579         .cm_clkmode_dpll_unipro = 0x4a0081c0,
 580         .cm_idlest_dpll_unipro = 0x4a0081c4,
 581         .cm_autoidle_dpll_unipro = 0x4a0081c8,
 582         .cm_clksel_dpll_unipro = 0x4a0081cc,
 583         .cm_div_m2_dpll_unipro = 0x4a0081d0,
 584         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
 585         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
 586         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
 587         .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
 588
 589         /* cm2.core */
 590         .cm_l3_1_clkstctrl = 0x4a008700,
 591         .cm_l3_1_dynamicdep = 0x4a008708,
 592         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
 593         .cm_l3_2_clkstctrl = 0x4a008800,
 594         .cm_l3_2_dynamicdep = 0x4a008808,
 595         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
 596         .cm_l3_gpmc_clkctrl = 0x4a008828,
 597         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
 598         .cm_mpu_m3_clkstctrl = 0x4a008900,
 599         .cm_mpu_m3_staticdep = 0x4a008904,
 600         .cm_mpu_m3_dynamicdep = 0x4a008908,
 601         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
 602         .cm_sdma_clkstctrl = 0x4a008a00,
 603         .cm_sdma_staticdep = 0x4a008a04,
 604         .cm_sdma_dynamicdep = 0x4a008a08,
 605         .cm_sdma_sdma_clkctrl = 0x4a008a20,
 606         .cm_memif_clkstctrl = 0x4a008b00,
 607         .cm_memif_dmm_clkctrl = 0x4a008b20,
 608         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
 609         .cm_memif_emif_1_clkctrl = 0x4a008b30,
 610         .cm_memif_emif_2_clkctrl = 0x4a008b38,
 611         .cm_memif_dll_clkctrl = 0x4a008b40,
 612         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
 613         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
 614         .cm_memif_dll_h_clkctrl = 0x4a008b60,
 615         .cm_c2c_clkstctrl = 0x4a008c00,
 616         .cm_c2c_staticdep = 0x4a008c04,
 617         .cm_c2c_dynamicdep = 0x4a008c08,
 618         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
 619         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
 620         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
 621         .cm_l4cfg_clkstctrl = 0x4a008d00,
 622         .cm_l4cfg_dynamicdep = 0x4a008d08,
 623         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
 624         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
 625         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
 626         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
 627         .cm_l3instr_clkstctrl = 0x4a008e00,
 628         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
 629         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
 630         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
 631         .cm_l4per_clkstctrl = 0x4a009000,
 632         .cm_l4per_dynamicdep = 0x4a009008,
 633         .cm_l4per_adc_clkctrl = 0x4a009020,
 634         .cm_l4per_gptimer10_clkctrl = 0x4a009028,
 635         .cm_l4per_gptimer11_clkctrl = 0x4a009030,
 636         .cm_l4per_gptimer2_clkctrl = 0x4a009038,
 637         .cm_l4per_gptimer3_clkctrl = 0x4a009040,
 638         .cm_l4per_gptimer4_clkctrl = 0x4a009048,
 639         .cm_l4per_gptimer9_clkctrl = 0x4a009050,
 640         .cm_l4per_elm_clkctrl = 0x4a009058,
 641         .cm_l4per_gpio2_clkctrl = 0x4a009060,
 642         .cm_l4per_gpio3_clkctrl = 0x4a009068,
 643         .cm_l4per_gpio4_clkctrl = 0x4a009070,
 644         .cm_l4per_gpio5_clkctrl = 0x4a009078,
 645         .cm_l4per_gpio6_clkctrl = 0x4a009080,
 646         .cm_l4per_hdq1w_clkctrl = 0x4a009088,
 647         .cm_l4per_hecc1_clkctrl = 0x4a009090,
 648         .cm_l4per_hecc2_clkctrl = 0x4a009098,
 649         .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
 650         .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
 651         .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
 652         .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
 653         .cm_l4per_l4per_clkctrl = 0x4a0090c0,
 654         .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
 655         .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
 656         .cm_l4per_mgate_clkctrl = 0x4a0090e8,
 657         .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
 658         .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
 659         .cm_l4per_mcspi3_clkctrl = 0x4a009100,
 660         .cm_l4per_mcspi4_clkctrl = 0x4a009108,
 661         .cm_l4per_gpio7_clkctrl = 0x4a009110,
 662         .cm_l4per_gpio8_clkctrl = 0x4a009118,
 663         .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
 664         .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
 665         .cm_l4per_msprohg_clkctrl = 0x4a009130,
 666         .cm_l4per_slimbus2_clkctrl = 0x4a009138,
 667         .cm_l4per_uart1_clkctrl = 0x4a009140,
 668         .cm_l4per_uart2_clkctrl = 0x4a009148,
 669         .cm_l4per_uart3_clkctrl = 0x4a009150,
 670         .cm_l4per_uart4_clkctrl = 0x4a009158,
 671         .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
 672         .cm_l4per_i2c5_clkctrl = 0x4a009168,
 673         .cm_l4per_uart5_clkctrl = 0x4a009170,
 674         .cm_l4per_uart6_clkctrl = 0x4a009178,
 675         .cm_l4sec_clkstctrl = 0x4a009180,
 676         .cm_l4sec_staticdep = 0x4a009184,
 677         .cm_l4sec_dynamicdep = 0x4a009188,
 678         .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
 679         .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
 680         .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
 681         .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
 682         .cm_l4sec_rng_clkctrl = 0x4a0091c0,
 683         .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
 684         .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
 685
 686         /* cm2.ivahd */
 687         .cm_ivahd_clkstctrl = 0x4a009200,
 688         .cm_ivahd_ivahd_clkctrl = 0x4a009220,
 689         .cm_ivahd_sl2_clkctrl = 0x4a009228,
 690
 691         /* cm2.cam */
 692         .cm_cam_clkstctrl = 0x4a009300,
 693         .cm_cam_iss_clkctrl = 0x4a009320,
 694         .cm_cam_fdif_clkctrl = 0x4a009328,
 695
 696         /* cm2.dss */
 697         .cm_dss_clkstctrl = 0x4a009400,
 698         .cm_dss_dss_clkctrl = 0x4a009420,
 699
 700         /* cm2.sgx */
 701         .cm_sgx_clkstctrl = 0x4a009500,
 702         .cm_sgx_sgx_clkctrl = 0x4a009520,
 703
 704         /* cm2.l3init */
 705         .cm_l3init_clkstctrl = 0x4a009600,
 706
 707         /* cm2.l3init */
 708         .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
 709         .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
 710         .cm_l3init_hsi_clkctrl = 0x4a009638,
 711         .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
 712         .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
 713         .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
 714         .cm_l3init_p1500_clkctrl = 0x4a009678,
 715         .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
 716         .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
 717
 718         /* prm irqstatus regs */
 719         .prm_irqstatus_mpu_2 = 0x4ae06014,
 720
 721         /* l4 wkup regs */
 722         .cm_abe_pll_ref_clksel = 0x4ae0610c,
 723         .cm_sys_clksel = 0x4ae06110,
 724         .cm_wkup_clkstctrl = 0x4ae07900,
 725         .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
 726         .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
 727         .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
 728         .cm_wkup_gpio1_clkctrl = 0x4ae07938,
 729         .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
 730         .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
 731         .cm_wkup_synctimer_clkctrl = 0x4ae07950,
 732         .cm_wkup_usim_clkctrl = 0x4ae07958,
 733         .cm_wkup_sarram_clkctrl = 0x4ae07960,
 734         .cm_wkup_keyboard_clkctrl = 0x4ae07978,
 735         .cm_wkup_rtc_clkctrl = 0x4ae07980,
 736         .cm_wkup_bandgap_clkctrl = 0x4ae07988,
 737         .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
 738         .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
 739         .prm_rstctrl = 0x4ae07c00,
 740         .prm_rstst = 0x4ae07c04,
 741         .prm_rsttime = 0x4ae07c08,
 742         .prm_vc_val_bypass = 0x4ae07ca0,
 743         .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
 744         .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
 745
 746         .prm_sldo_core_setup = 0x4ae07cc4,
 747         .prm_sldo_core_ctrl = 0x4ae07cc8,
 748         .prm_sldo_mpu_setup = 0x4ae07ccc,
 749         .prm_sldo_mpu_ctrl = 0x4ae07cd0,
 750         .prm_sldo_mm_setup = 0x4ae07cd4,
 751         .prm_sldo_mm_ctrl = 0x4ae07cd8,
 752         .prm_abbldo_mpu_setup = 0x4ae07cdc,
 753         .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
 754 };
 755
 756 struct prcm_regs const dra7xx_prcm = {
 757         /* cm1.ckgen */
 758         .cm_clksel_core                         = 0x4a005100,
 759         .cm_clksel_abe                          = 0x4a005108,
 760         .cm_dll_ctrl                            = 0x4a005110,
 761         .cm_clkmode_dpll_core                   = 0x4a005120,
 762         .cm_idlest_dpll_core                    = 0x4a005124,
 763         .cm_autoidle_dpll_core                  = 0x4a005128,
 764         .cm_clksel_dpll_core                    = 0x4a00512c,
 765         .cm_div_m2_dpll_core                    = 0x4a005130,
 766         .cm_div_m3_dpll_core                    = 0x4a005134,
 767         .cm_div_h11_dpll_core                   = 0x4a005138,
 768         .cm_div_h12_dpll_core                   = 0x4a00513c,
 769         .cm_div_h13_dpll_core                   = 0x4a005140,
 770         .cm_div_h14_dpll_core                   = 0x4a005144,
 771         .cm_ssc_deltamstep_dpll_core            = 0x4a005148,
 772         .cm_ssc_modfreqdiv_dpll_core            = 0x4a00514c,
 773         .cm_div_h21_dpll_core                   = 0x4a005150,
 774         .cm_div_h22_dpllcore                    = 0x4a005154,
 775         .cm_div_h23_dpll_core                   = 0x4a005158,
 776         .cm_div_h24_dpll_core                   = 0x4a00515c,
 777         .cm_clkmode_dpll_mpu                    = 0x4a005160,
 778         .cm_idlest_dpll_mpu                     = 0x4a005164,
 779         .cm_autoidle_dpll_mpu                   = 0x4a005168,
 780         .cm_clksel_dpll_mpu                     = 0x4a00516c,
 781         .cm_div_m2_dpll_mpu                     = 0x4a005170,
 782         .cm_ssc_deltamstep_dpll_mpu             = 0x4a005188,
 783         .cm_ssc_modfreqdiv_dpll_mpu             = 0x4a00518c,
 784         .cm_bypclk_dpll_mpu                     = 0x4a00519c,
 785         .cm_clkmode_dpll_iva                    = 0x4a0051a0,
 786         .cm_idlest_dpll_iva                     = 0x4a0051a4,
 787         .cm_autoidle_dpll_iva                   = 0x4a0051a8,
 788         .cm_clksel_dpll_iva                     = 0x4a0051ac,
 789         .cm_ssc_deltamstep_dpll_iva             = 0x4a0051c8,
 790         .cm_ssc_modfreqdiv_dpll_iva             = 0x4a0051cc,
 791         .cm_bypclk_dpll_iva                     = 0x4a0051dc,
 792         .cm_clkmode_dpll_abe                    = 0x4a0051e0,
 793         .cm_idlest_dpll_abe                     = 0x4a0051e4,
 794         .cm_autoidle_dpll_abe                   = 0x4a0051e8,
 795         .cm_clksel_dpll_abe                     = 0x4a0051ec,
 796         .cm_div_m2_dpll_abe                     = 0x4a0051f0,
 797         .cm_div_m3_dpll_abe                     = 0x4a0051f4,
 798         .cm_ssc_deltamstep_dpll_abe             = 0x4a005208,
 799         .cm_ssc_modfreqdiv_dpll_abe             = 0x4a00520c,
 800         .cm_clkmode_dpll_ddrphy                 = 0x4a005210,
 801         .cm_idlest_dpll_ddrphy                  = 0x4a005214,
 802         .cm_autoidle_dpll_ddrphy                = 0x4a005218,
 803         .cm_clksel_dpll_ddrphy                  = 0x4a00521c,
 804         .cm_div_m2_dpll_ddrphy                  = 0x4a005220,
 805         .cm_div_h11_dpll_ddrphy                 = 0x4a005228,
 806         .cm_ssc_deltamstep_dpll_ddrphy          = 0x4a00522c,
 807         .cm_clkmode_dpll_dsp                    = 0x4a005234,
 808         .cm_shadow_freq_config1                 = 0x4a005260,
 809
 810         /* cm1.mpu */
 811         .cm_mpu_mpu_clkctrl                     = 0x4a005320,
 812
 813         /* cm1.dsp */
 814         .cm_dsp_clkstctrl                       = 0x4a005400,
 815         .cm_dsp_dsp_clkctrl                     = 0x4a005420,
 816
 817         /* cm2.ckgen */
 818         .cm_clksel_usb_60mhz                    = 0x4a008104,
 819         .cm_clkmode_dpll_per                    = 0x4a008140,
 820         .cm_idlest_dpll_per                     = 0x4a008144,
 821         .cm_autoidle_dpll_per                   = 0x4a008148,
 822         .cm_clksel_dpll_per                     = 0x4a00814c,
 823         .cm_div_m2_dpll_per                     = 0x4a008150,
 824         .cm_div_m3_dpll_per                     = 0x4a008154,
 825         .cm_div_h11_dpll_per                    = 0x4a008158,
 826         .cm_div_h12_dpll_per                    = 0x4a00815c,
 827         .cm_div_h13_dpll_per                    = 0x4a008160,
 828         .cm_div_h14_dpll_per                    = 0x4a008164,
 829         .cm_ssc_deltamstep_dpll_per             = 0x4a008168,
 830         .cm_ssc_modfreqdiv_dpll_per             = 0x4a00816c,
 831         .cm_clkmode_dpll_usb                    = 0x4a008180,
 832         .cm_idlest_dpll_usb                     = 0x4a008184,
 833         .cm_autoidle_dpll_usb                   = 0x4a008188,
 834         .cm_clksel_dpll_usb                     = 0x4a00818c,
 835         .cm_div_m2_dpll_usb                     = 0x4a008190,
 836         .cm_ssc_deltamstep_dpll_usb             = 0x4a0081a8,
 837         .cm_ssc_modfreqdiv_dpll_usb             = 0x4a0081ac,
 838         .cm_clkdcoldo_dpll_usb                  = 0x4a0081b4,
 839         .cm_clkmode_dpll_pcie_ref               = 0x4a008200,
 840         .cm_clkmode_apll_pcie                   = 0x4a00821c,
 841         .cm_idlest_apll_pcie                    = 0x4a008220,
 842         .cm_div_m2_apll_pcie                    = 0x4a008224,
 843         .cm_clkvcoldo_apll_pcie                 = 0x4a008228,
 844
 845         /* cm2.core */
 846         .cm_l3_1_clkstctrl                      = 0x4a008700,
 847         .cm_l3_1_dynamicdep                     = 0x4a008708,
 848         .cm_l3_1_l3_1_clkctrl                   = 0x4a008720,
 849         .cm_l3_gpmc_clkctrl                     = 0x4a008728,
 850         .cm_mpu_m3_clkstctrl                    = 0x4a008900,
 851         .cm_mpu_m3_staticdep                    = 0x4a008904,
 852         .cm_mpu_m3_dynamicdep                   = 0x4a008908,
 853         .cm_mpu_m3_mpu_m3_clkctrl               = 0x4a008920,
 854         .cm_sdma_clkstctrl                      = 0x4a008a00,
 855         .cm_sdma_staticdep                      = 0x4a008a04,
 856         .cm_sdma_dynamicdep                     = 0x4a008a08,
 857         .cm_sdma_sdma_clkctrl                   = 0x4a008a20,
 858         .cm_memif_clkstctrl                     = 0x4a008b00,
 859         .cm_memif_dmm_clkctrl                   = 0x4a008b20,
 860         .cm_memif_emif_fw_clkctrl               = 0x4a008b28,
 861         .cm_memif_emif_1_clkctrl                = 0x4a008b30,
 862         .cm_memif_emif_2_clkctrl                = 0x4a008b38,
 863         .cm_memif_dll_clkctrl                   = 0x4a008b40,
 864         .cm_l4cfg_clkstctrl                     = 0x4a008d00,
 865         .cm_l4cfg_dynamicdep                    = 0x4a008d08,
 866         .cm_l4cfg_l4_cfg_clkctrl                = 0x4a008d20,
 867         .cm_l4cfg_hw_sem_clkctrl                = 0x4a008d28,
 868         .cm_l4cfg_mailbox_clkctrl               = 0x4a008d30,
 869         .cm_l4cfg_sar_rom_clkctrl               = 0x4a008d38,
 870         .cm_l3instr_clkstctrl                   = 0x4a008e00,
 871         .cm_l3instr_l3_3_clkctrl                = 0x4a008e20,
 872         .cm_l3instr_l3_instr_clkctrl            = 0x4a008e28,
 873         .cm_l3instr_intrconn_wp1_clkctrl        = 0x4a008e40,
 874
 875         /* cm2.ivahd */
 876         .cm_ivahd_clkstctrl                     = 0x4a008f00,
 877         .cm_ivahd_ivahd_clkctrl                 = 0x4a008f20,
 878         .cm_ivahd_sl2_clkctrl                   = 0x4a008f28,
 879
 880         /* cm2.cam */
 881         .cm_cam_clkstctrl                       = 0x4a009000,
 882         .cm_cam_vip1_clkctrl                    = 0x4a009020,
 883         .cm_cam_vip2_clkctrl                    = 0x4a009028,
 884         .cm_cam_vip3_clkctrl                    = 0x4a009030,
 885         .cm_cam_lvdsrx_clkctrl                  = 0x4a009038,
 886         .cm_cam_csi1_clkctrl                    = 0x4a009040,
 887         .cm_cam_csi2_clkctrl                    = 0x4a009048,
 888
 889         /* cm2.dss */
 890         .cm_dss_clkstctrl                       = 0x4a009100,
 891         .cm_dss_dss_clkctrl                     = 0x4a009120,
 892
 893         /* cm2.sgx */
 894         .cm_sgx_clkstctrl                       = 0x4a009200,
 895         .cm_sgx_sgx_clkctrl                     = 0x4a009220,
 896
 897         /* cm2.l3init */
 898         .cm_l3init_clkstctrl                    = 0x4a009300,
 899
 900         /* cm2.l3init */
 901         .cm_l3init_hsmmc1_clkctrl               = 0x4a009328,
 902         .cm_l3init_hsmmc2_clkctrl               = 0x4a009330,
 903         .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
 904         .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
 905         .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
 906         .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
 907
 908         /* cm2.l4per */
 909         .cm_l4per_clkstctrl                     = 0x4a009700,
 910         .cm_l4per_dynamicdep                    = 0x4a009708,
 911         .cm_l4per_gptimer10_clkctrl             = 0x4a009728,
 912         .cm_l4per_gptimer11_clkctrl             = 0x4a009730,
 913         .cm_l4per_gptimer2_clkctrl              = 0x4a009738,
 914         .cm_l4per_gptimer3_clkctrl              = 0x4a009740,
 915         .cm_l4per_gptimer4_clkctrl              = 0x4a009748,
 916         .cm_l4per_gptimer9_clkctrl              = 0x4a009750,
 917         .cm_l4per_elm_clkctrl                   = 0x4a009758,
 918         .cm_l4per_gpio2_clkctrl                 = 0x4a009760,
 919         .cm_l4per_gpio3_clkctrl                 = 0x4a009768,
 920         .cm_l4per_gpio4_clkctrl                 = 0x4a009770,
 921         .cm_l4per_gpio5_clkctrl                 = 0x4a009778,
 922         .cm_l4per_gpio6_clkctrl                 = 0x4a009780,
 923         .cm_l4per_hdq1w_clkctrl                 = 0x4a009788,
 924         .cm_l4per_i2c1_clkctrl                  = 0x4a0097a0,
 925         .cm_l4per_i2c2_clkctrl                  = 0x4a0097a8,
 926         .cm_l4per_i2c3_clkctrl                  = 0x4a0097b0,
 927         .cm_l4per_i2c4_clkctrl                  = 0x4a0097b8,
 928         .cm_l4per_l4per_clkctrl                 = 0x4a0097c0,
 929         .cm_l4per_mcspi1_clkctrl                = 0x4a0097f0,
 930         .cm_l4per_mcspi2_clkctrl                = 0x4a0097f8,
 931         .cm_l4per_mcspi3_clkctrl                = 0x4a009800,
 932         .cm_l4per_mcspi4_clkctrl                = 0x4a009808,
 933         .cm_l4per_gpio7_clkctrl                 = 0x4a009810,
 934         .cm_l4per_gpio8_clkctrl                 = 0x4a009818,
 935         .cm_l4per_mmcsd3_clkctrl                = 0x4a009820,
 936         .cm_l4per_mmcsd4_clkctrl                = 0x4a009828,
 937         .cm_l4per_uart1_clkctrl                 = 0x4a009840,
 938         .cm_l4per_uart2_clkctrl                 = 0x4a009848,
 939         .cm_l4per_uart3_clkctrl                 = 0x4a009850,
 940         .cm_l4per_uart4_clkctrl                 = 0x4a009858,
 941         .cm_l4per_uart5_clkctrl                 = 0x4a009870,
 942         .cm_l4sec_clkstctrl                     = 0x4a009880,
 943         .cm_l4sec_staticdep                     = 0x4a009884,
 944         .cm_l4sec_dynamicdep                    = 0x4a009888,
 945         .cm_l4sec_aes1_clkctrl                  = 0x4a0098a0,
 946         .cm_l4sec_aes2_clkctrl                  = 0x4a0098a8,
 947         .cm_l4sec_des3des_clkctrl               = 0x4a0098b0,
 948         .cm_l4sec_rng_clkctrl                   = 0x4a0098c0,
 949         .cm_l4sec_sha2md51_clkctrl              = 0x4a0098c8,
 950         .cm_l4sec_cryptodma_clkctrl             = 0x4a0098d8,
 951
 952         /* l4 wkup regs */
 953         .cm_abe_pll_ref_clksel                  = 0x4ae0610c,
 954         .cm_sys_clksel                          = 0x4ae06110,
 955         .cm_abe_pll_sys_clksel                  = 0x4ae06118,
 956         .cm_wkup_clkstctrl                      = 0x4ae07800,
 957         .cm_wkup_l4wkup_clkctrl                 = 0x4ae07820,
 958         .cm_wkup_wdtimer1_clkctrl               = 0x4ae07828,
 959         .cm_wkup_wdtimer2_clkctrl               = 0x4ae07830,
 960         .cm_wkup_gpio1_clkctrl                  = 0x4ae07838,
 961         .cm_wkup_gptimer1_clkctrl               = 0x4ae07840,
 962         .cm_wkup_gptimer12_clkctrl              = 0x4ae07848,
 963         .cm_wkup_sarram_clkctrl                 = 0x4ae07860,
 964         .cm_wkup_keyboard_clkctrl               = 0x4ae07878,
 965         .cm_wkupaon_scrm_clkctrl                = 0x4ae07890,
 966         .prm_rstctrl                            = 0x4ae07d00,
 967         .prm_rstst                              = 0x4ae07d04,
 968         .prm_rsttime                            = 0x4ae07d08,
 969         .prm_vc_val_bypass                      = 0x4ae07da0,
 970         .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
 971         .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,
 972 };