2 * Timing and Organization details of the ddr device parts used in OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/sys_proto.h>
18 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
19 * EVM. Since the parts used and geometry are identical for
20 * evm for a given OMAP5 revision, this information is kept
21 * here instead of being in board directory. However the key functions
22 * exported are weakly linked so that they can be over-ridden in the board
23 * directory if there is a OMAP5 board in the future that uses a different
24 * memory device or geometry.
26 * For any new board with different memory devices over-ride one or more
27 * of the following functions as per the CONFIG flags you intend to enable:
28 * - emif_get_reg_dump()
29 * - emif_get_dmm_regs()
30 * - emif_get_device_details()
31 * - emif_get_device_timings()
34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
35 const struct emif_regs emif_regs_532_mhz_2cs
= {
36 .sdram_config_init
= 0x80800EBA,
37 .sdram_config
= 0x808022BA,
38 .ref_ctrl
= 0x0000081A,
39 .sdram_tim1
= 0x772F6873,
40 .sdram_tim2
= 0x304a129a,
41 .sdram_tim3
= 0x02f7e45f,
42 .read_idle_ctrl
= 0x00050000,
43 .zq_config
= 0x000b3215,
44 .temp_alert_config
= 0x08000a05,
45 .emif_ddr_phy_ctlr_1_init
= 0x0E28420d,
46 .emif_ddr_phy_ctlr_1
= 0x0E28420d,
47 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
48 .emif_ddr_ext_phy_ctrl_2
= 0x28C518A3,
49 .emif_ddr_ext_phy_ctrl_3
= 0x518A3146,
50 .emif_ddr_ext_phy_ctrl_4
= 0x0014628C,
51 .emif_ddr_ext_phy_ctrl_5
= 0x04010040
54 const struct emif_regs emif_regs_532_mhz_2cs_es2
= {
55 .sdram_config_init
= 0x80800EBA,
56 .sdram_config
= 0x808022BA,
57 .ref_ctrl
= 0x0000081A,
58 .sdram_tim1
= 0x772F6873,
59 .sdram_tim2
= 0x304a129a,
60 .sdram_tim3
= 0x02f7e45f,
61 .read_idle_ctrl
= 0x00050000,
62 .zq_config
= 0x100b3215,
63 .temp_alert_config
= 0x08000a05,
64 .emif_ddr_phy_ctlr_1_init
= 0x0E30400d,
65 .emif_ddr_phy_ctlr_1
= 0x0E30400d,
66 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
67 .emif_ddr_ext_phy_ctrl_2
= 0x28C518A3,
68 .emif_ddr_ext_phy_ctrl_3
= 0x518A3146,
69 .emif_ddr_ext_phy_ctrl_4
= 0x0014628C,
70 .emif_ddr_ext_phy_ctrl_5
= 0xC330CC33,
73 const struct emif_regs emif_regs_266_mhz_2cs
= {
74 .sdram_config_init
= 0x80800EBA,
75 .sdram_config
= 0x808022BA,
76 .ref_ctrl
= 0x0000040D,
77 .sdram_tim1
= 0x2A86B419,
78 .sdram_tim2
= 0x1025094A,
79 .sdram_tim3
= 0x026BA22F,
80 .read_idle_ctrl
= 0x00050000,
81 .zq_config
= 0x000b3215,
82 .temp_alert_config
= 0x08000a05,
83 .emif_ddr_phy_ctlr_1_init
= 0x0E28420d,
84 .emif_ddr_phy_ctlr_1
= 0x0E28420d,
85 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
86 .emif_ddr_ext_phy_ctrl_2
= 0x0A414829,
87 .emif_ddr_ext_phy_ctrl_3
= 0x14829052,
88 .emif_ddr_ext_phy_ctrl_4
= 0x000520A4,
89 .emif_ddr_ext_phy_ctrl_5
= 0x04010040
92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs
= {
93 .sdram_config_init
= 0x61851B32,
94 .sdram_config
= 0x61851B32,
96 .ref_ctrl
= 0x00001035,
97 .sdram_tim1
= 0xCCCF36B3,
98 .sdram_tim2
= 0x308F7FDA,
99 .sdram_tim3
= 0x027F88A8,
100 .read_idle_ctrl
= 0x00050000,
101 .zq_config
= 0x0007190B,
102 .temp_alert_config
= 0x00000000,
103 .emif_ddr_phy_ctlr_1_init
= 0x0020420A,
104 .emif_ddr_phy_ctlr_1
= 0x0024420A,
105 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
106 .emif_ddr_ext_phy_ctrl_2
= 0x00000000,
107 .emif_ddr_ext_phy_ctrl_3
= 0x00000000,
108 .emif_ddr_ext_phy_ctrl_4
= 0x00000000,
109 .emif_ddr_ext_phy_ctrl_5
= 0x04010040,
110 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
111 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
112 .emif_rd_wr_lvl_ctl
= 0x00000000,
113 .emif_rd_wr_exec_thresh
= 0x00000305
116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2
= {
117 .sdram_config_init
= 0x61851B32,
118 .sdram_config
= 0x61851B32,
119 .sdram_config2
= 0x0,
120 .ref_ctrl
= 0x00001035,
121 .sdram_tim1
= 0xCCCF36B3,
122 .sdram_tim2
= 0x308F7FDA,
123 .sdram_tim3
= 0x027F88A8,
124 .read_idle_ctrl
= 0x00050000,
125 .zq_config
= 0x1007190B,
126 .temp_alert_config
= 0x00000000,
127 .emif_ddr_phy_ctlr_1_init
= 0x0030400A,
128 .emif_ddr_phy_ctlr_1
= 0x0034400A,
129 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
130 .emif_ddr_ext_phy_ctrl_2
= 0x00000000,
131 .emif_ddr_ext_phy_ctrl_3
= 0x00000000,
132 .emif_ddr_ext_phy_ctrl_4
= 0x00000000,
133 .emif_ddr_ext_phy_ctrl_5
= 0x4350D435,
134 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
135 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
136 .emif_rd_wr_lvl_ctl
= 0x00000000,
137 .emif_rd_wr_exec_thresh
= 0x40000305
140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1
= {
141 .sdram_config_init
= 0x61851ab2,
142 .sdram_config
= 0x61851ab2,
143 .sdram_config2
= 0x08000000,
144 .ref_ctrl
= 0x000040F1,
145 .ref_ctrl_final
= 0x00001035,
146 .sdram_tim1
= 0xCCCF36B3,
147 .sdram_tim2
= 0x308F7FDA,
148 .sdram_tim3
= 0x027F88A8,
149 .read_idle_ctrl
= 0x00050001,
150 .zq_config
= 0x0007190B,
151 .temp_alert_config
= 0x00000000,
152 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
153 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
154 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
155 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
156 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
157 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
158 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
159 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
160 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
161 .emif_rd_wr_lvl_ctl
= 0x00000000,
162 .emif_rd_wr_exec_thresh
= 0x00000305
165 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1
= {
166 .sdram_config_init
= 0x61851B32,
167 .sdram_config
= 0x61851B32,
168 .sdram_config2
= 0x08000000,
169 .ref_ctrl
= 0x000040F1,
170 .ref_ctrl_final
= 0x00001035,
171 .sdram_tim1
= 0xCCCF36B3,
172 .sdram_tim2
= 0x308F7FDA,
173 .sdram_tim3
= 0x027F88A8,
174 .read_idle_ctrl
= 0x00050001,
175 .zq_config
= 0x0007190B,
176 .temp_alert_config
= 0x00000000,
177 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
178 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
179 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
180 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
181 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
182 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
183 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
184 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
185 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
186 .emif_rd_wr_lvl_ctl
= 0x00000000,
187 .emif_rd_wr_exec_thresh
= 0x00000305
190 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1
= {
191 .sdram_config_init
= 0x61862B32,
192 .sdram_config
= 0x61862B32,
193 .sdram_config2
= 0x08000000,
194 .ref_ctrl
= 0x0000514C,
195 .ref_ctrl_final
= 0x0000144A,
196 .sdram_tim1
= 0xD113781C,
197 .sdram_tim2
= 0x305A7FDA,
198 .sdram_tim3
= 0x409F86A8,
199 .read_idle_ctrl
= 0x00050000,
200 .zq_config
= 0x5007190B,
201 .temp_alert_config
= 0x00000000,
202 .emif_ddr_phy_ctlr_1_init
= 0x0024400D,
203 .emif_ddr_phy_ctlr_1
= 0x0E24400D,
204 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
205 .emif_ddr_ext_phy_ctrl_2
= 0x00A400A4,
206 .emif_ddr_ext_phy_ctrl_3
= 0x00A900A9,
207 .emif_ddr_ext_phy_ctrl_4
= 0x00B000B0,
208 .emif_ddr_ext_phy_ctrl_5
= 0x00B000B0,
209 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
210 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
211 .emif_rd_wr_lvl_ctl
= 0x00000000,
212 .emif_rd_wr_exec_thresh
= 0x00000305
215 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2
= {
216 .dmm_lisa_map_0
= 0x0,
217 .dmm_lisa_map_1
= 0x0,
218 .dmm_lisa_map_2
= 0x80740300,
219 .dmm_lisa_map_3
= 0xFF020100,
224 * DRA752 EVM board has 1.5 GB of memory
225 * EMIF1 --> 2Gb * 2 = 512MB
226 * EMIF2 --> 2Gb * 4 = 1GB
227 * so mapping 1GB interleaved and 512MB non-interleaved
229 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2
= {
230 .dmm_lisa_map_0
= 0x0,
231 .dmm_lisa_map_1
= 0x80640300,
232 .dmm_lisa_map_2
= 0xC0500220,
233 .dmm_lisa_map_3
= 0xFF020100,
238 * DRA752 EVM EMIF1 ONLY CONFIGURATION
240 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2
= {
241 .dmm_lisa_map_0
= 0x0,
242 .dmm_lisa_map_1
= 0x0,
243 .dmm_lisa_map_2
= 0x80500100,
244 .dmm_lisa_map_3
= 0xFF020100,
249 * DRA752 EVM EMIF2 ONLY CONFIGURATION
251 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2
= {
252 .dmm_lisa_map_0
= 0x0,
253 .dmm_lisa_map_1
= 0x0,
254 .dmm_lisa_map_2
= 0x80600200,
255 .dmm_lisa_map_3
= 0xFF020100,
260 * DRA722 EVM EMIF1 CONFIGURATION
262 const struct dmm_lisa_map_regs lisa_map_2G_x_2
= {
263 .dmm_lisa_map_0
= 0x0,
264 .dmm_lisa_map_1
= 0x0,
265 .dmm_lisa_map_2
= 0x80600100,
266 .dmm_lisa_map_3
= 0xFF020100,
270 static void emif_get_reg_dump_sdp(u32 emif_nr
, const struct emif_regs
**regs
)
272 switch (omap_revision()) {
274 *regs
= &emif_regs_532_mhz_2cs
;
277 *regs
= &emif_regs_ddr3_532_mhz_1cs
;
280 *regs
= &emif_regs_532_mhz_2cs_es2
;
283 *regs
= &emif_regs_ddr3_532_mhz_1cs_es2
;
289 *regs
= &emif_1_regs_ddr3_532_mhz_1cs_dra_es1
;
292 *regs
= &emif_2_regs_ddr3_532_mhz_1cs_dra_es1
;
297 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra_es1
;
300 *regs
= &emif_1_regs_ddr3_532_mhz_1cs_dra_es1
;
304 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
305 __attribute__((weak
, alias("emif_get_reg_dump_sdp")));
307 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
310 switch (omap_revision()) {
315 *dmm_lisa_regs
= &lisa_map_4G_x_2_x_2
;
319 *dmm_lisa_regs
= &lisa_map_2G_x_2_x_2_2G_x_1_x_2
;
323 *dmm_lisa_regs
= &lisa_map_2G_x_2
;
328 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
329 __attribute__((weak
, alias("emif_get_dmm_regs_sdp")));
332 static const struct lpddr2_device_details dev_4G_S4_details
= {
333 .type
= LPDDR2_TYPE_S4
,
334 .density
= LPDDR2_DENSITY_4Gb
,
335 .io_width
= LPDDR2_IO_WIDTH_32
,
336 .manufacturer
= LPDDR2_MANUFACTURER_SAMSUNG
339 static void emif_get_device_details_sdp(u32 emif_nr
,
340 struct lpddr2_device_details
*cs0_device_details
,
341 struct lpddr2_device_details
*cs1_device_details
)
343 /* EMIF1 & EMIF2 have identical configuration */
344 *cs0_device_details
= dev_4G_S4_details
;
345 *cs1_device_details
= dev_4G_S4_details
;
348 void emif_get_device_details(u32 emif_nr
,
349 struct lpddr2_device_details
*cs0_device_details
,
350 struct lpddr2_device_details
*cs1_device_details
)
351 __attribute__((weak
, alias("emif_get_device_details_sdp")));
353 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
355 const u32 ext_phy_ctrl_const_base
[] = {
378 const u32 ddr3_ext_phy_ctrl_const_base_es1
[] = {
401 const u32 ddr3_ext_phy_ctrl_const_base_es2
[] = {
424 /* Ext phy ctrl 1-35 regs */
426 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
[] = {
464 /* Ext phy ctrl 1-35 regs */
466 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
[] = {
504 /* Ext phy ctrl 1-35 regs */
506 dra_ddr3_ext_phy_ctrl_const_base_666MHz
[] = {
544 const struct lpddr2_mr_regs mr_regs
= {
545 .mr1
= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8
,
548 .mr10
= MR10_ZQ_ZQINIT
,
549 .mr16
= MR16_REF_FULL_ARRAY
552 void __weak
emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
,
556 switch (omap_revision()) {
559 *regs
= ext_phy_ctrl_const_base
;
560 *size
= ARRAY_SIZE(ext_phy_ctrl_const_base
);
563 *regs
= ddr3_ext_phy_ctrl_const_base_es1
;
564 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1
);
567 *regs
= ddr3_ext_phy_ctrl_const_base_es2
;
568 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2
);
573 *regs
= dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
;
575 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
);
577 *regs
= dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
;
579 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
);
583 *regs
= dra_ddr3_ext_phy_ctrl_const_base_666MHz
;
584 *size
= ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz
);
587 *regs
= ddr3_ext_phy_ctrl_const_base_es2
;
588 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2
);
593 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs
**regs
)
598 static void do_ext_phy_settings_omap5(u32 base
, const struct emif_regs
*regs
)
600 u32
*ext_phy_ctrl_base
= 0;
601 u32
*emif_ext_phy_ctrl_base
= 0;
603 const u32
*ext_phy_ctrl_const_regs
;
607 emif_nr
= (base
== EMIF1_BASE
) ? 1 : 2;
609 struct emif_reg_struct
*emif
= (struct emif_reg_struct
*)base
;
611 ext_phy_ctrl_base
= (u32
*) &(regs
->emif_ddr_ext_phy_ctrl_1
);
612 emif_ext_phy_ctrl_base
= (u32
*) &(emif
->emif_ddr_ext_phy_ctrl_1
);
614 /* Configure external phy control timing registers */
615 for (i
= 0; i
< EMIF_EXT_PHY_CTRL_TIMING_REG
; i
++) {
616 writel(*ext_phy_ctrl_base
, emif_ext_phy_ctrl_base
++);
617 /* Update shadow registers */
618 writel(*ext_phy_ctrl_base
++, emif_ext_phy_ctrl_base
++);
622 * external phy 6-24 registers do not change with
625 emif_get_ext_phy_ctrl_const_regs(emif_nr
,
626 &ext_phy_ctrl_const_regs
, &size
);
628 for (i
= 0; i
< size
; i
++) {
629 writel(ext_phy_ctrl_const_regs
[i
],
630 emif_ext_phy_ctrl_base
++);
631 /* Update shadow registers */
632 writel(ext_phy_ctrl_const_regs
[i
],
633 emif_ext_phy_ctrl_base
++);
637 static void do_ext_phy_settings_dra7(u32 base
, const struct emif_regs
*regs
)
639 struct emif_reg_struct
*emif
= (struct emif_reg_struct
*)base
;
640 u32
*emif_ext_phy_ctrl_base
= 0;
642 const u32
*ext_phy_ctrl_const_regs
;
643 u32 i
, hw_leveling
, size
;
645 emif_nr
= (base
== EMIF1_BASE
) ? 1 : 2;
647 hw_leveling
= regs
->emif_rd_wr_lvl_rmp_ctl
>> EMIF_REG_RDWRLVL_EN_SHIFT
;
649 emif_ext_phy_ctrl_base
= (u32
*)&(emif
->emif_ddr_ext_phy_ctrl_1
);
651 emif_get_ext_phy_ctrl_const_regs(emif_nr
,
652 &ext_phy_ctrl_const_regs
, &size
);
654 writel(ext_phy_ctrl_const_regs
[0], &emif_ext_phy_ctrl_base
[0]);
655 writel(ext_phy_ctrl_const_regs
[0], &emif_ext_phy_ctrl_base
[1]);
659 * Copy the predefined PHY register values
660 * in case of sw leveling
662 for (i
= 1; i
< 25; i
++) {
663 writel(ext_phy_ctrl_const_regs
[i
],
664 &emif_ext_phy_ctrl_base
[i
* 2]);
665 writel(ext_phy_ctrl_const_regs
[i
],
666 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
670 * Write the init value for HW levling to occur
672 for (i
= 21; i
< 35; i
++) {
673 writel(ext_phy_ctrl_const_regs
[i
],
674 &emif_ext_phy_ctrl_base
[i
* 2]);
675 writel(ext_phy_ctrl_const_regs
[i
],
676 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
681 void do_ext_phy_settings(u32 base
, const struct emif_regs
*regs
)
684 do_ext_phy_settings_omap5(base
, regs
);
686 do_ext_phy_settings_dra7(base
, regs
);
689 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
690 static const struct lpddr2_ac_timings timings_jedec_532_mhz
= {
691 .max_freq
= 532000000,
713 static const struct lpddr2_min_tck min_tck
= {
728 static const struct lpddr2_ac_timings
*ac_timings
[MAX_NUM_SPEEDBINS
] = {
729 &timings_jedec_532_mhz
732 static const struct lpddr2_device_timings dev_4G_S4_timings
= {
733 .ac_timings
= ac_timings
,
738 * List of status registers to be controlled back to control registers
739 * after initial leveling
742 const struct read_write_regs omap5_bug_00339_regs
[] = {
757 const struct read_write_regs dra_bug_00339_regs
[] = {
780 const struct read_write_regs
*get_bug_regs(u32
*iterations
)
782 const struct read_write_regs
*bug_00339_regs_ptr
= NULL
;
784 switch (omap_revision()) {
789 bug_00339_regs_ptr
= omap5_bug_00339_regs
;
790 *iterations
= sizeof(omap5_bug_00339_regs
)/
791 sizeof(omap5_bug_00339_regs
[0]);
796 bug_00339_regs_ptr
= dra_bug_00339_regs
;
797 *iterations
= sizeof(dra_bug_00339_regs
)/
798 sizeof(dra_bug_00339_regs
[0]);
801 printf("\n Error: UnKnown SOC");
804 return bug_00339_regs_ptr
;
807 void emif_get_device_timings_sdp(u32 emif_nr
,
808 const struct lpddr2_device_timings
**cs0_device_timings
,
809 const struct lpddr2_device_timings
**cs1_device_timings
)
811 /* Identical devices on EMIF1 & EMIF2 */
812 *cs0_device_timings
= &dev_4G_S4_timings
;
813 *cs1_device_timings
= &dev_4G_S4_timings
;
816 void emif_get_device_timings(u32 emif_nr
,
817 const struct lpddr2_device_timings
**cs0_device_timings
,
818 const struct lpddr2_device_timings
**cs1_device_timings
)
819 __attribute__((weak
, alias("emif_get_device_timings_sdp")));
821 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */