arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm/emif.h>
  31 #include <asm/arch/sys_proto.h>
  32
  33 /*
  34  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  35  * EVM. Since the parts used and geometry are identical for
  36  * evm for a given OMAP5 revision, this information is kept
  37  * here instead of being in board directory. However the key functions
  38  * exported are weakly linked so that they can be over-ridden in the board
  39  * directory if there is a OMAP5 board in the future that uses a different
  40  * memory device or geometry.
  41  *
  42  * For any new board with different memory devices over-ride one or more
  43  * of the following functions as per the CONFIG flags you intend to enable:
  44  * - emif_get_reg_dump()
  45  * - emif_get_dmm_regs()
  46  * - emif_get_device_details()
  47  * - emif_get_device_timings()
  48  */
  49
  50 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  51 const struct emif_regs emif_regs_532_mhz_2cs = {
  52         .sdram_config_init              = 0x80800EBA,
  53         .sdram_config                   = 0x808022BA,
  54         .ref_ctrl                       = 0x0000081A,
  55         .sdram_tim1                     = 0x772F6873,
  56         .sdram_tim2                     = 0x304a129a,
  57         .sdram_tim3                     = 0x02f7e45f,
  58         .read_idle_ctrl                 = 0x00050000,
  59         .zq_config                      = 0x000b3215,
  60         .temp_alert_config              = 0x08000a05,
  61         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  62         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  63         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  64         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  65         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  66         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  67         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  68 };
  69
  70 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  71         .sdram_config_init              = 0x80800EBA,
  72         .sdram_config                   = 0x808022BA,
  73         .ref_ctrl                       = 0x0000081A,
  74         .sdram_tim1                     = 0x772F6873,
  75         .sdram_tim2                     = 0x304a129a,
  76         .sdram_tim3                     = 0x02f7e45f,
  77         .read_idle_ctrl                 = 0x00050000,
  78         .zq_config                      = 0x100b3215,
  79         .temp_alert_config              = 0x08000a05,
  80         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  81         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  82         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  83         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  84         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  85         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  86         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  87 };
  88
  89 const struct emif_regs emif_regs_266_mhz_2cs = {
  90         .sdram_config_init              = 0x80800EBA,
  91         .sdram_config                   = 0x808022BA,
  92         .ref_ctrl                       = 0x0000040D,
  93         .sdram_tim1                     = 0x2A86B419,
  94         .sdram_tim2                     = 0x1025094A,
  95         .sdram_tim3                     = 0x026BA22F,
  96         .read_idle_ctrl                 = 0x00050000,
  97         .zq_config                      = 0x000b3215,
  98         .temp_alert_config              = 0x08000a05,
  99         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
 100         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
 101         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
 102         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
 103         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
 104         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
 105         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 106 };
 107
 108 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
 109         .sdram_config_init              = 0x61851B32,
 110         .sdram_config                   = 0x61851B32,
 111         .sdram_config2                  = 0x0,
 112         .ref_ctrl                       = 0x00001035,
 113         .sdram_tim1                     = 0xCCCF36B3,
 114         .sdram_tim2                     = 0x308F7FDA,
 115         .sdram_tim3                     = 0x027F88A8,
 116         .read_idle_ctrl                 = 0x00050000,
 117         .zq_config                      = 0x0007190B,
 118         .temp_alert_config              = 0x00000000,
 119         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 120         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 121         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 122         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 123         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 124         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 125         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 126         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 127         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 128         .emif_rd_wr_lvl_ctl             = 0x00000000,
 129         .emif_rd_wr_exec_thresh         = 0x00000305
 130 };
 131
 132 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 133         .sdram_config_init              = 0x61851B32,
 134         .sdram_config                   = 0x61851B32,
 135         .sdram_config2                  = 0x0,
 136         .ref_ctrl                       = 0x00001035,
 137         .sdram_tim1                     = 0xCCCF36B3,
 138         .sdram_tim2                     = 0x308F7FDA,
 139         .sdram_tim3                     = 0x027F88A8,
 140         .read_idle_ctrl                 = 0x00050000,
 141         .zq_config                      = 0x1007190B,
 142         .temp_alert_config              = 0x00000000,
 143         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 144         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 145         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 146         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 147         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 148         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 149         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 150         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 151         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 152         .emif_rd_wr_lvl_ctl             = 0x00000000,
 153         .emif_rd_wr_exec_thresh         = 0x40000305
 154 };
 155
 156 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 157         .sdram_config_init              = 0x61851ab2,
 158         .sdram_config                   = 0x61851ab2,
 159         .sdram_config2                  = 0x08000000,
 160         .ref_ctrl                       = 0x00001035,
 161         .sdram_tim1                     = 0xCCCF36B3,
 162         .sdram_tim2                     = 0x308F7FDA,
 163         .sdram_tim3                     = 0x027F88A8,
 164         .read_idle_ctrl                 = 0x00050000,
 165         .zq_config                      = 0x0007190B,
 166         .temp_alert_config              = 0x00000000,
 167         .emif_ddr_phy_ctlr_1_init       = 0x0E20400A,
 168         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 169         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 170         .emif_ddr_ext_phy_ctrl_2        = 0x009E009E,
 171         .emif_ddr_ext_phy_ctrl_3        = 0x009E009E,
 172         .emif_ddr_ext_phy_ctrl_4        = 0x009E009E,
 173         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 174         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 175         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 176         .emif_rd_wr_lvl_ctl             = 0x00000000,
 177         .emif_rd_wr_exec_thresh         = 0x00000305
 178 };
 179
 180 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 181         .sdram_config_init              = 0x61851B32,
 182         .sdram_config                   = 0x61851B32,
 183         .sdram_config2                  = 0x08000000,
 184         .ref_ctrl                       = 0x00001035,
 185         .sdram_tim1                     = 0xCCCF36B3,
 186         .sdram_tim2                     = 0x308F7FDA,
 187         .sdram_tim3                     = 0x027F88A8,
 188         .read_idle_ctrl                 = 0x00050000,
 189         .zq_config                      = 0x0007190B,
 190         .temp_alert_config              = 0x00000000,
 191         .emif_ddr_phy_ctlr_1_init       = 0x0020400A,
 192         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 193         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 194         .emif_ddr_ext_phy_ctrl_2        = 0x009D009D,
 195         .emif_ddr_ext_phy_ctrl_3        = 0x009D009D,
 196         .emif_ddr_ext_phy_ctrl_4        = 0x009D009D,
 197         .emif_ddr_ext_phy_ctrl_5        = 0x009D009D,
 198         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 199         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 200         .emif_rd_wr_lvl_ctl             = 0x00000000,
 201         .emif_rd_wr_exec_thresh         = 0x00000305
 202 };
 203
 204 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 205         .dmm_lisa_map_0 = 0x0,
 206         .dmm_lisa_map_1 = 0x0,
 207         .dmm_lisa_map_2 = 0x80740300,
 208         .dmm_lisa_map_3 = 0xFF020100,
 209         .is_ma_present  = 0x1
 210 };
 211
 212 /*
 213  * DRA752 EVM board has 1.5 GB of memory
 214  * EMIF1 --> 2Gb * 2 =  512MB
 215  * EMIF2 --> 2Gb * 4 =  1GB
 216  * so mapping 1GB interleaved and 512MB non-interleaved
 217  */
 218 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 219         .dmm_lisa_map_0 = 0x0,
 220         .dmm_lisa_map_1 = 0x80640300,
 221         .dmm_lisa_map_2 = 0xC0500220,
 222         .dmm_lisa_map_3 = 0xFF020100,
 223         .is_ma_present  = 0x1
 224 };
 225
 226 /*
 227  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 228  */
 229 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 230         .dmm_lisa_map_0 = 0x0,
 231         .dmm_lisa_map_1 = 0x0,
 232         .dmm_lisa_map_2 = 0x80500100,
 233         .dmm_lisa_map_3 = 0xFF020100,
 234         .is_ma_present  = 0x1
 235 };
 236
 237 /*
 238  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 239  */
 240 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 241         .dmm_lisa_map_0 = 0x0,
 242         .dmm_lisa_map_1 = 0x0,
 243         .dmm_lisa_map_2 = 0x80600200,
 244         .dmm_lisa_map_3 = 0xFF020100,
 245         .is_ma_present  = 0x1
 246 };
 247
 248 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 249 {
 250         switch (omap_revision()) {
 251         case OMAP5430_ES1_0:
 252                 *regs = &emif_regs_532_mhz_2cs;
 253                 break;
 254         case OMAP5432_ES1_0:
 255                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 256                 break;
 257         case OMAP5430_ES2_0:
 258                 *regs = &emif_regs_532_mhz_2cs_es2;
 259                 break;
 260         case OMAP5432_ES2_0:
 261                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 262                 break;
 263         case DRA752_ES1_0:
 264                 switch (emif_nr) {
 265                 case 1:
 266                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 267                         break;
 268                 case 2:
 269                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 270                         break;
 271                 }
 272                 break;
 273         default:
 274                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 275         }
 276 }
 277
 278 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 279         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 280
 281 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 282                                                 **dmm_lisa_regs)
 283 {
 284         switch (omap_revision()) {
 285         case OMAP5430_ES1_0:
 286         case OMAP5430_ES2_0:
 287         case OMAP5432_ES1_0:
 288         case OMAP5432_ES2_0:
 289                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 290                 break;
 291         case DRA752_ES1_0:
 292         default:
 293                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 294         }
 295
 296 }
 297
 298 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 299         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 300 #else
 301
 302 static const struct lpddr2_device_details dev_4G_S4_details = {
 303         .type           = LPDDR2_TYPE_S4,
 304         .density        = LPDDR2_DENSITY_4Gb,
 305         .io_width       = LPDDR2_IO_WIDTH_32,
 306         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 307 };
 308
 309 static void emif_get_device_details_sdp(u32 emif_nr,
 310                 struct lpddr2_device_details *cs0_device_details,
 311                 struct lpddr2_device_details *cs1_device_details)
 312 {
 313         /* EMIF1 & EMIF2 have identical configuration */
 314         *cs0_device_details = dev_4G_S4_details;
 315         *cs1_device_details = dev_4G_S4_details;
 316 }
 317
 318 void emif_get_device_details(u32 emif_nr,
 319                 struct lpddr2_device_details *cs0_device_details,
 320                 struct lpddr2_device_details *cs1_device_details)
 321         __attribute__((weak, alias("emif_get_device_details_sdp")));
 322
 323 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 324
 325 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 326         0x01004010,
 327         0x00001004,
 328         0x04010040,
 329         0x01004010,
 330         0x00001004,
 331         0x00000000,
 332         0x00000000,
 333         0x00000000,
 334         0x80080080,
 335         0x00800800,
 336         0x08102040,
 337         0x00000001,
 338         0x540A8150,
 339         0xA81502a0,
 340         0x002A0540,
 341         0x00000000,
 342         0x00000000,
 343         0x00000000,
 344         0x00000077,
 345         0x0
 346 };
 347
 348 const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 349         0x01004010,
 350         0x00001004,
 351         0x04010040,
 352         0x01004010,
 353         0x00001004,
 354         0x00000000,
 355         0x00000000,
 356         0x00000000,
 357         0x80080080,
 358         0x00800800,
 359         0x08102040,
 360         0x00000002,
 361         0x0,
 362         0x0,
 363         0x0,
 364         0x00000000,
 365         0x00000000,
 366         0x00000000,
 367         0x00000057,
 368         0x0
 369 };
 370
 371 const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 372         0x50D4350D,
 373         0x00000D43,
 374         0x04010040,
 375         0x01004010,
 376         0x00001004,
 377         0x00000000,
 378         0x00000000,
 379         0x00000000,
 380         0x80080080,
 381         0x00800800,
 382         0x08102040,
 383         0x00000002,
 384         0x00000000,
 385         0x00000000,
 386         0x00000000,
 387         0x00000000,
 388         0x00000000,
 389         0x00000000,
 390         0x00000057,
 391         0x0
 392 };
 393
 394 const u32
 395 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 396         0x009E009E,
 397         0x002E002E,
 398         0x002E002E,
 399         0x002E002E,
 400         0x002E002E,
 401         0x002E002E,
 402         0x004D004D,
 403         0x004D004D,
 404         0x004D004D,
 405         0x004D004D,
 406         0x004D004D,
 407         0x004D004D,
 408         0x004D004D,
 409         0x004D004D,
 410         0x004D004D,
 411         0x004D004D,
 412         0x0,
 413         0x600020,
 414         0x40010080,
 415         0x8102040
 416 };
 417
 418 const u32
 419 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 420         0x009D009D,
 421         0x002D002D,
 422         0x002D002D,
 423         0x002D002D,
 424         0x002D002D,
 425         0x002D002D,
 426         0x00570057,
 427         0x00570057,
 428         0x00570057,
 429         0x00570057,
 430         0x00570057,
 431         0x00570057,
 432         0x00570057,
 433         0x00570057,
 434         0x00570057,
 435         0x00570057,
 436         0x0,
 437         0x600020,
 438         0x40010080,
 439         0x8102040
 440 };
 441
 442 const struct lpddr2_mr_regs mr_regs = {
 443         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 444         .mr2    = 0x6,
 445         .mr3    = 0x1,
 446         .mr10   = MR10_ZQ_ZQINIT,
 447         .mr16   = MR16_REF_FULL_ARRAY
 448 };
 449
 450 static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
 451 {
 452         switch (omap_revision()) {
 453         case OMAP5430_ES1_0:
 454         case OMAP5430_ES2_0:
 455                 *regs = ext_phy_ctrl_const_base;
 456                 break;
 457         case OMAP5432_ES1_0:
 458                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 459                 break;
 460         case OMAP5432_ES2_0:
 461                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 462                 break;
 463         case DRA752_ES1_0:
 464                 if (emif_nr == 1)
 465                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 466                 else
 467                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 468                 break;
 469         default:
 470                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 471
 472         }
 473 }
 474
 475 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 476 {
 477         *regs = &mr_regs;
 478 }
 479
 480 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 481 {
 482         u32 *ext_phy_ctrl_base = 0;
 483         u32 *emif_ext_phy_ctrl_base = 0;
 484         u32 emif_nr;
 485         const u32 *ext_phy_ctrl_const_regs;
 486         u32 i = 0;
 487
 488         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 489
 490         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 491
 492         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 493         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 494
 495         /* Configure external phy control timing registers */
 496         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 497                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 498                 /* Update shadow registers */
 499                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 500         }
 501
 502         /*
 503          * external phy 6-24 registers do not change with
 504          * ddr frequency
 505          */
 506         emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
 507         for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
 508                 writel(ext_phy_ctrl_const_regs[i],
 509                        emif_ext_phy_ctrl_base++);
 510                 /* Update shadow registers */
 511                 writel(ext_phy_ctrl_const_regs[i],
 512                        emif_ext_phy_ctrl_base++);
 513         }
 514 }
 515
 516 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 517 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 518         .max_freq       = 532000000,
 519         .RL             = 8,
 520         .tRPab          = 21,
 521         .tRCD           = 18,
 522         .tWR            = 15,
 523         .tRASmin        = 42,
 524         .tRRD           = 10,
 525         .tWTRx2         = 15,
 526         .tXSR           = 140,
 527         .tXPx2          = 15,
 528         .tRFCab         = 130,
 529         .tRTPx2         = 15,
 530         .tCKE           = 3,
 531         .tCKESR         = 15,
 532         .tZQCS          = 90,
 533         .tZQCL          = 360,
 534         .tZQINIT        = 1000,
 535         .tDQSCKMAXx2    = 11,
 536         .tRASmax        = 70,
 537         .tFAW           = 50
 538 };
 539
 540 static const struct lpddr2_min_tck min_tck = {
 541         .tRL            = 3,
 542         .tRP_AB         = 3,
 543         .tRCD           = 3,
 544         .tWR            = 3,
 545         .tRAS_MIN       = 3,
 546         .tRRD           = 2,
 547         .tWTR           = 2,
 548         .tXP            = 2,
 549         .tRTP           = 2,
 550         .tCKE           = 3,
 551         .tCKESR         = 3,
 552         .tFAW           = 8
 553 };
 554
 555 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 556         &timings_jedec_532_mhz
 557 };
 558
 559 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 560         .ac_timings     = ac_timings,
 561         .min_tck        = &min_tck,
 562 };
 563
 564 void emif_get_device_timings_sdp(u32 emif_nr,
 565                 const struct lpddr2_device_timings **cs0_device_timings,
 566                 const struct lpddr2_device_timings **cs1_device_timings)
 567 {
 568         /* Identical devices on EMIF1 & EMIF2 */
 569         *cs0_device_timings = &dev_4G_S4_timings;
 570         *cs1_device_timings = &dev_4G_S4_timings;
 571 }
 572
 573 void emif_get_device_timings(u32 emif_nr,
 574                 const struct lpddr2_device_timings **cs0_device_timings,
 575                 const struct lpddr2_device_timings **cs1_device_timings)
 576         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 577
 578 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */