arch/arm/cpu/armv7/socfpga/lowlevel_init.S

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <version.h>
   9
  10 /* Save the parameter pass in by previous boot loader */
  11 .global save_boot_params
  12 save_boot_params:
  13         /* save the parameter here */
  14
  15         /*
  16          * Setup stack for exception, which is located
  17          * at the end of on-chip RAM. We don't expect exception prior to
  18          * relocation and if that happens, we won't worry -- it will overide
  19          * global data region as the code will goto reset. After relocation,
  20          * this region won't be used by other part of program.
  21          * Hence it is safe.
  22          */
  23         ldr     r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  24         ldr     r1, =IRQ_STACK_START_IN
  25         str     r0, [r1]
  26
  27         bx      lr
  28
  29
  30 /* Set up the platform, once the cpu has been initialized */
  31 .globl lowlevel_init
  32 lowlevel_init:
  33
  34         /* Remap */
  35 #ifdef CONFIG_SPL_BUILD
  36         /*
  37          * SPL : configure the remap (L3 NIC-301 GPV)
  38          * so the on-chip RAM at lower memory instead ROM.
  39          */
  40         ldr     r0, =SOCFPGA_L3REGS_ADDRESS
  41         mov     r1, #0x19
  42         str     r1, [r0]
  43 #else
  44         /*
  45          * U-Boot : configure the remap (L3 NIC-301 GPV)
  46          * so the SDRAM at lower memory instead on-chip RAM.
  47          */
  48         ldr     r0, =SOCFPGA_L3REGS_ADDRESS
  49         mov     r1, #0x2
  50         str     r1, [r0]
  51
  52         /* Private components security */
  53
  54         /*
  55          * U-Boot : configure private timer, global timer and cpu
  56          * component access as non secure for kernel stage (as required
  57          * by kernel)
  58          */
  59         mrc     p15,4,r0,c15,c0,0
  60         add     r1, r0, #0x54
  61         ldr     r2, [r1]
  62         orr     r2, r2, #0xff
  63         orr     r2, r2, #0xf00
  64         str     r2, [r1]
  65 #endif  /* #ifdef CONFIG_SPL_BUILD */
  66         mov     pc, lr