arch/arm/cpu/armv7/start.S

   1 /*
   2  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
   3  *
   4  * Copyright (c) 2004   Texas Instruments <r-woodruff2@ti.com>
   5  *
   6  * Copyright (c) 2001   Marius Gröger <mag@sysgo.de>
   7  * Copyright (c) 2002   Alex Züpke <azu@sysgo.de>
   8  * Copyright (c) 2002   Gary Jennejohn <garyj@denx.de>
   9  * Copyright (c) 2003   Richard Woodruff <r-woodruff2@ti.com>
  10  * Copyright (c) 2003   Kshitij <kshitij@ti.com>
  11  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <asm-offsets.h>
  17 #include <config.h>
  18 #include <version.h>
  19 #include <asm/system.h>
  20 #include <linux/linkage.h>
  21
  22 /*************************************************************************
  23  *
  24  * Startup Code (reset vector)
  25  *
  26  * do important init only if we don't start from memory!
  27  * setup Memory and board specific bits prior to relocation.
  28  * relocate armboot to ram
  29  * setup stack
  30  *
  31  *************************************************************************/
  32
  33         .globl  reset
  34
  35 reset:
  36         bl      save_boot_params
  37         /*
  38          * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
  39          * except if in HYP mode already
  40          */
  41         mrs     r0, cpsr
  42         and     r1, r0, #0x1f           @ mask mode bits
  43         teq     r1, #0x1a               @ test for HYP mode
  44         bicne   r0, r0, #0x1f           @ clear all mode bits
  45         orrne   r0, r0, #0x13           @ set SVC mode
  46         orr     r0, r0, #0xc0           @ disable FIQ and IRQ
  47         msr     cpsr,r0
  48
  49 /*
  50  * Setup vector:
  51  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  52  * Continue to use ROM code vector only in OMAP4 spl)
  53  */
  54 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
  55         /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
  56         mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
  57         bic     r0, #CR_V               @ V = 0
  58         mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
  59
  60         /* Set vector address in CP15 VBAR register */
  61         ldr     r0, =_start
  62         mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
  63 #endif
  64
  65         /* the mask ROM code should have PLL and others stable */
  66 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  67         bl      cpu_init_cp15
  68         bl      cpu_init_crit
  69 #endif
  70
  71         bl      _main
  72
  73 /*------------------------------------------------------------------------------*/
  74
  75 ENTRY(c_runtime_cpu_setup)
  76 /*
  77  * If I-cache is enabled invalidate it
  78  */
  79 #ifndef CONFIG_SYS_ICACHE_OFF
  80         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
  81         mcr     p15, 0, r0, c7, c10, 4  @ DSB
  82         mcr     p15, 0, r0, c7, c5, 4   @ ISB
  83 #endif
  84 /*
  85  * Move vector table
  86  */
  87         /* Set vector address in CP15 VBAR register */
  88         ldr     r0, =_start
  89         mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
  90
  91         bx      lr
  92
  93 ENDPROC(c_runtime_cpu_setup)
  94
  95 /*************************************************************************
  96  *
  97  * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  98  *      __attribute__((weak));
  99  *
 100  * Stack pointer is not yet initialized at this moment
 101  * Don't save anything to stack even if compiled with -O0
 102  *
 103  *************************************************************************/
 104 ENTRY(save_boot_params)
 105         bx      lr                      @ back to my caller
 106 ENDPROC(save_boot_params)
 107         .weak   save_boot_params
 108
 109 /*************************************************************************
 110  *
 111  * cpu_init_cp15
 112  *
 113  * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
 114  * CONFIG_SYS_ICACHE_OFF is defined.
 115  *
 116  *************************************************************************/
 117 ENTRY(cpu_init_cp15)
 118         /*
 119          * Invalidate L1 I/D
 120          */
 121         mov     r0, #0                  @ set up for MCR
 122         mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
 123         mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
 124         mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
 125         mcr     p15, 0, r0, c7, c10, 4  @ DSB
 126         mcr     p15, 0, r0, c7, c5, 4   @ ISB
 127
 128         /*
 129          * disable MMU stuff and caches
 130          */
 131         mrc     p15, 0, r0, c1, c0, 0
 132         bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
 133         bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
 134         orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
 135         orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
 136 #ifdef CONFIG_SYS_ICACHE_OFF
 137         bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
 138 #else
 139         orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
 140 #endif
 141         mcr     p15, 0, r0, c1, c0, 0
 142
 143 #ifdef CONFIG_ARM_ERRATA_716044
 144         mrc     p15, 0, r0, c1, c0, 0   @ read system control register
 145         orr     r0, r0, #1 << 11        @ set bit #11
 146         mcr     p15, 0, r0, c1, c0, 0   @ write system control register
 147 #endif
 148
 149 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
 150         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 151         orr     r0, r0, #1 << 4         @ set bit #4
 152         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 153 #endif
 154
 155 #ifdef CONFIG_ARM_ERRATA_743622
 156         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 157         orr     r0, r0, #1 << 6         @ set bit #6
 158         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 159 #endif
 160
 161 #ifdef CONFIG_ARM_ERRATA_751472
 162         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 163         orr     r0, r0, #1 << 11        @ set bit #11
 164         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 165 #endif
 166 #ifdef CONFIG_ARM_ERRATA_761320
 167         mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
 168         orr     r0, r0, #1 << 21        @ set bit #21
 169         mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 170 #endif
 171
 172         mov     pc, lr                  @ back to my caller
 173 ENDPROC(cpu_init_cp15)
 174
 175 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 176 /*************************************************************************
 177  *
 178  * CPU_init_critical registers
 179  *
 180  * setup important registers
 181  * setup memory timing
 182  *
 183  *************************************************************************/
 184 ENTRY(cpu_init_crit)
 185         /*
 186          * Jump to board specific initialization...
 187          * The Mask ROM will have already initialized
 188          * basic memory. Go here to bump up clock rate and handle
 189          * wake up conditions.
 190          */
 191         b       lowlevel_init           @ go setup pll,mux,memory
 192 ENDPROC(cpu_init_crit)
 193 #endif