arch/arm/cpu/armv7/sunxi/board.c

   1 /*
   2  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  *
   4  * (C) Copyright 2007-2011
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * Some init for sunxi platform.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <i2c.h>
  15 #include <serial.h>
  16 #ifdef CONFIG_SPL_BUILD
  17 #include <spl.h>
  18 #endif
  19 #include <asm/gpio.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/timer.h>
  25
  26 #include <linux/compiler.h>
  27
  28 struct fel_stash {
  29         uint32_t sp;
  30         uint32_t lr;
  31         uint32_t cpsr;
  32         uint32_t sctlr;
  33         uint32_t vbar;
  34         uint32_t cr;
  35 };
  36
  37 struct fel_stash fel_stash __attribute__((section(".data")));
  38
  39 static int gpio_init(void)
  40 {
  41 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  42 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  43         /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  44         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  45         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  46 #endif
  47 #if defined(CONFIG_MACH_SUN8I)
  48         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
  49         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
  50 #else
  51         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
  52         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
  53 #endif
  54         sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  55 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
  56         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  57         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  58         sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  59 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  60         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  61         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  62         sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  63 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  64         sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  65         sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  66         sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  67 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
  68         sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
  69         sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
  70         sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
  71 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
  72         sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
  73         sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
  74         sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
  75 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
  76         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
  77         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
  78         sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
  79 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
  80         sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
  81         sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
  82         sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
  83 #else
  84 #error Unsupported console port number. Please fix pin mux settings in board.c
  85 #endif
  86
  87         return 0;
  88 }
  89
  90 void spl_board_load_image(void)
  91 {
  92         debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
  93         return_to_fel(fel_stash.sp, fel_stash.lr);
  94 }
  95
  96 void s_init(void)
  97 {
  98 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
  99         /* Magic (undocmented) value taken from boot0, without this DRAM
 100          * access gets messed up (seems cache related) */
 101         setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 102 #endif
 103 #if defined CONFIG_MACH_SUN6I || \
 104     defined CONFIG_MACH_SUN7I || \
 105     defined CONFIG_MACH_SUN8I
 106         /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 107         asm volatile(
 108                 "mrc p15, 0, r0, c1, c0, 1\n"
 109                 "orr r0, r0, #1 << 6\n"
 110                 "mcr p15, 0, r0, c1, c0, 1\n");
 111 #endif
 112
 113         clock_init();
 114         timer_init();
 115         gpio_init();
 116         i2c_init_board();
 117 }
 118
 119 #ifdef CONFIG_SPL_BUILD
 120 /* The sunxi internal brom will try to loader external bootloader
 121  * from mmc0, nand flash, mmc2.
 122  *
 123  * Unfortunately we can't check how SPL was loaded so assume it's
 124  * always the first SD/MMC controller, unless it was explicitly
 125  * stated that SPL is on nand flash.
 126  */
 127 u32 spl_boot_device(void)
 128 {
 129 #if defined(CONFIG_SPL_NAND_SUPPORT)
 130         /*
 131          * This is compile time configuration informing SPL, that it
 132          * was loaded from nand flash.
 133          */
 134         return BOOT_DEVICE_NAND;
 135 #else
 136         /*
 137          * When booting from the SD card, the "eGON.BT0" signature is expected
 138          * to be found in memory at the address 0x0004 (see the "mksunxiboot"
 139          * tool, which generates this header).
 140          *
 141          * When booting in the FEL mode over USB, this signature is patched in
 142          * memory and replaced with something else by the 'fel' tool. This other
 143          * signature is selected in such a way, that it can't be present in a
 144          * valid bootable SD card image (because the BROM would refuse to
 145          * execute the SPL in this case).
 146          *
 147          * This branch is just making a decision at runtime whether to load
 148          * the main u-boot binary from the SD card (if the "eGON.BT0" signature
 149          * is found) or return to the FEL code in the BROM to wait and receive
 150          * the main u-boot binary over USB.
 151          */
 152         if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
 153                 return BOOT_DEVICE_MMC1;
 154         else
 155                 return BOOT_DEVICE_BOARD;
 156 #endif
 157 }
 158
 159 /* No confirmation data available in SPL yet. Hardcode bootmode */
 160 u32 spl_boot_mode(void)
 161 {
 162         return MMCSD_MODE_RAW;
 163 }
 164
 165 void board_init_f(ulong dummy)
 166 {
 167         preloader_console_init();
 168
 169 #ifdef CONFIG_SPL_I2C_SUPPORT
 170         /* Needed early by sunxi_board_init if PMU is enabled */
 171         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 172 #endif
 173         sunxi_board_init();
 174
 175         /* Clear the BSS. */
 176         memset(__bss_start, 0, __bss_end - __bss_start);
 177
 178         board_init_r(NULL, 0);
 179 }
 180 #endif
 181
 182 void reset_cpu(ulong addr)
 183 {
 184 #ifdef CONFIG_SUNXI_GEN_SUN4I
 185         static const struct sunxi_wdog *wdog =
 186                  &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 187
 188         /* Set the watchdog for its shortest interval (.5s) and wait */
 189         writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 190         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 191
 192         while (1) {
 193                 /* sun5i sometimes gets stuck without this */
 194                 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 195         }
 196 #endif
 197 #ifdef CONFIG_SUNXI_GEN_SUN6I
 198         static const struct sunxi_wdog *wdog =
 199                  ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 200
 201         /* Set the watchdog for its shortest interval (.5s) and wait */
 202         writel(WDT_CFG_RESET, &wdog->cfg);
 203         writel(WDT_MODE_EN, &wdog->mode);
 204         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 205 #endif
 206 }
 207
 208 #ifndef CONFIG_SYS_DCACHE_OFF
 209 void enable_caches(void)
 210 {
 211         /* Enable D-cache. I-cache is already enabled in start.S */
 212         dcache_enable();
 213 }
 214 #endif
 215
 216 #ifdef CONFIG_CMD_NET
 217 /*
 218  * Initializes on-chip ethernet controllers.
 219  * to override, implement board_eth_init()
 220  */
 221 int cpu_eth_init(bd_t *bis)
 222 {
 223         __maybe_unused int rc;
 224
 225 #ifdef CONFIG_MACPWR
 226         gpio_direction_output(CONFIG_MACPWR, 1);
 227         mdelay(200);
 228 #endif
 229
 230 #ifdef CONFIG_SUNXI_GMAC
 231         rc = sunxi_gmac_initialize(bis);
 232         if (rc < 0) {
 233                 printf("sunxi: failed to initialize gmac\n");
 234                 return rc;
 235         }
 236 #endif
 237
 238         return 0;
 239 }
 240 #endif