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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
2 * sun8i H3 platform dram controller init
4 * (C) Copyright 2007-2015 Allwinner Technology Co.
5 * Jerry Wang <wangflord@allwinnertech.com>
6 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
7 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
8 * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/dram.h>
16 #include <linux/kconfig.h>
27 static inline int ns_to_t(int nanoseconds
)
29 const unsigned int ctrl_freq
= CONFIG_DRAM_CLK
/ 2;
31 return DIV_ROUND_UP(ctrl_freq
* nanoseconds
, 1000);
34 static u32
bin_to_mgray(int val
)
36 static const u8 lookup_table
[32] = {
37 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
38 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
39 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
40 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
43 return lookup_table
[clamp(val
, 0, 31)];
46 static int mgray_to_bin(u32 val
)
48 static const u8 lookup_table
[32] = {
49 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
50 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
51 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
52 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
55 return lookup_table
[val
& 0x1f];
58 static void mctl_phy_init(u32 val
)
60 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
61 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
63 writel(val
| PIR_INIT
, &mctl_ctl
->pir
);
64 mctl_await_completion(&mctl_ctl
->pgsr
[0], PGSR_INIT_DONE
, 0x1);
67 static void mctl_dq_delay(u32 read
, u32 write
)
69 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
70 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
74 for (i
= 0; i
< 4; i
++) {
75 val
= DATX_IOCR_WRITE_DELAY((write
>> (i
* 4)) & 0xf) |
76 DATX_IOCR_READ_DELAY(((read
>> (i
* 4)) & 0xf) * 2);
78 for (j
= DATX_IOCR_DQ(0); j
<= DATX_IOCR_DM
; j
++)
79 writel(val
, &mctl_ctl
->datx
[i
].iocr
[j
]);
82 clrbits_le32(&mctl_ctl
->pgcr
[0], 1 << 26);
84 for (i
= 0; i
< 4; i
++) {
85 val
= DATX_IOCR_WRITE_DELAY((write
>> (16 + i
* 4)) & 0xf) |
86 DATX_IOCR_READ_DELAY((read
>> (16 + i
* 4)) & 0xf);
88 writel(val
, &mctl_ctl
->datx
[i
].iocr
[DATX_IOCR_DQS
]);
89 writel(val
, &mctl_ctl
->datx
[i
].iocr
[DATX_IOCR_DQSN
]);
92 setbits_le32(&mctl_ctl
->pgcr
[0], 1 << 26);
97 static void mctl_set_master_priority(void)
99 struct sunxi_mctl_com_reg
* const mctl_com
=
100 (struct sunxi_mctl_com_reg
*)SUNXI_DRAM_COM_BASE
;
102 /* enable bandwidth limit windows and set windows size 1us */
103 writel(0x00010190, &mctl_com
->bwcr
);
105 /* set cpu high priority */
106 writel(0x00000001, &mctl_com
->mapr
);
108 writel(0x0200000d, &mctl_com
->mcr
[0][0]);
109 writel(0x00800100, &mctl_com
->mcr
[0][1]);
110 writel(0x06000009, &mctl_com
->mcr
[1][0]);
111 writel(0x01000400, &mctl_com
->mcr
[1][1]);
112 writel(0x0200000d, &mctl_com
->mcr
[2][0]);
113 writel(0x00600100, &mctl_com
->mcr
[2][1]);
114 writel(0x0100000d, &mctl_com
->mcr
[3][0]);
115 writel(0x00200080, &mctl_com
->mcr
[3][1]);
116 writel(0x07000009, &mctl_com
->mcr
[4][0]);
117 writel(0x01000640, &mctl_com
->mcr
[4][1]);
118 writel(0x0100000d, &mctl_com
->mcr
[5][0]);
119 writel(0x00200080, &mctl_com
->mcr
[5][1]);
120 writel(0x01000009, &mctl_com
->mcr
[6][0]);
121 writel(0x00400080, &mctl_com
->mcr
[6][1]);
122 writel(0x0100000d, &mctl_com
->mcr
[7][0]);
123 writel(0x00400080, &mctl_com
->mcr
[7][1]);
124 writel(0x0100000d, &mctl_com
->mcr
[8][0]);
125 writel(0x00400080, &mctl_com
->mcr
[8][1]);
126 writel(0x04000009, &mctl_com
->mcr
[9][0]);
127 writel(0x00400100, &mctl_com
->mcr
[9][1]);
128 writel(0x2000030d, &mctl_com
->mcr
[10][0]);
129 writel(0x04001800, &mctl_com
->mcr
[10][1]);
130 writel(0x04000009, &mctl_com
->mcr
[11][0]);
131 writel(0x00400120, &mctl_com
->mcr
[11][1]);
134 static void mctl_set_timing_params(struct dram_para
*para
)
136 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
137 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
140 u8 tfaw
= ns_to_t(50);
141 u8 trrd
= max(ns_to_t(10), 4);
142 u8 trcd
= ns_to_t(15);
143 u8 trc
= ns_to_t(53);
144 u8 txp
= max(ns_to_t(8), 3);
145 u8 twtr
= max(ns_to_t(8), 4);
146 u8 trtp
= max(ns_to_t(8), 4);
147 u8 twr
= max(ns_to_t(15), 3);
148 u8 trp
= ns_to_t(15);
149 u8 tras
= ns_to_t(38);
150 u16 trefi
= ns_to_t(7800) / 32;
151 u16 trfc
= ns_to_t(350);
162 u8 tcl
= 6; /* CL 12 */
163 u8 tcwl
= 4; /* CWL 8 */
167 u32 tdinit0
= (500 * CONFIG_DRAM_CLK
) + 1; /* 500us */
168 u32 tdinit1
= (360 * CONFIG_DRAM_CLK
) / 1000 + 1; /* 360ns */
169 u32 tdinit2
= (200 * CONFIG_DRAM_CLK
) + 1; /* 200us */
170 u32 tdinit3
= (1 * CONFIG_DRAM_CLK
) + 1; /* 1us */
172 u8 twtp
= tcwl
+ 2 + twr
; /* WL + BL / 2 + tWR */
173 u8 twr2rd
= tcwl
+ 2 + twtr
; /* WL + BL / 2 + tWTR */
174 u8 trd2wr
= tcl
+ 2 + 1 - tcwl
; /* RL + BL / 2 + 2 - WL */
176 /* set mode register */
177 writel(0x1c70, &mctl_ctl
->mr
[0]); /* CL=11, WR=12 */
178 writel(0x40, &mctl_ctl
->mr
[1]);
179 writel(0x18, &mctl_ctl
->mr
[2]); /* CWL=8 */
180 writel(0x0, &mctl_ctl
->mr
[3]);
182 /* set DRAM timing */
183 writel(DRAMTMG0_TWTP(twtp
) | DRAMTMG0_TFAW(tfaw
) |
184 DRAMTMG0_TRAS_MAX(trasmax
) | DRAMTMG0_TRAS(tras
),
185 &mctl_ctl
->dramtmg
[0]);
186 writel(DRAMTMG1_TXP(txp
) | DRAMTMG1_TRTP(trtp
) | DRAMTMG1_TRC(trc
),
187 &mctl_ctl
->dramtmg
[1]);
188 writel(DRAMTMG2_TCWL(tcwl
) | DRAMTMG2_TCL(tcl
) |
189 DRAMTMG2_TRD2WR(trd2wr
) | DRAMTMG2_TWR2RD(twr2rd
),
190 &mctl_ctl
->dramtmg
[2]);
191 writel(DRAMTMG3_TMRW(tmrw
) | DRAMTMG3_TMRD(tmrd
) | DRAMTMG3_TMOD(tmod
),
192 &mctl_ctl
->dramtmg
[3]);
193 writel(DRAMTMG4_TRCD(trcd
) | DRAMTMG4_TCCD(tccd
) | DRAMTMG4_TRRD(trrd
) |
194 DRAMTMG4_TRP(trp
), &mctl_ctl
->dramtmg
[4]);
195 writel(DRAMTMG5_TCKSRX(tcksrx
) | DRAMTMG5_TCKSRE(tcksre
) |
196 DRAMTMG5_TCKESR(tckesr
) | DRAMTMG5_TCKE(tcke
),
197 &mctl_ctl
->dramtmg
[5]);
199 /* set two rank timing */
200 clrsetbits_le32(&mctl_ctl
->dramtmg
[8], (0xff << 8) | (0xff << 0),
201 (0x66 << 8) | (0x10 << 0));
203 /* set PHY interface timing, write latency and read latency configure */
204 writel((0x2 << 24) | (t_rdata_en
<< 16) | (0x1 << 8) |
205 (wr_latency
<< 0), &mctl_ctl
->pitmg
[0]);
207 /* set PHY timing, PTR0-2 use default */
208 writel(PTR3_TDINIT0(tdinit0
) | PTR3_TDINIT1(tdinit1
), &mctl_ctl
->ptr
[3]);
209 writel(PTR4_TDINIT2(tdinit2
) | PTR4_TDINIT3(tdinit3
), &mctl_ctl
->ptr
[4]);
211 /* set refresh timing */
212 writel(RFSHTMG_TREFI(trefi
) | RFSHTMG_TRFC(trfc
), &mctl_ctl
->rfshtmg
);
215 static void mctl_zq_calibration(struct dram_para
*para
)
217 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
218 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
224 writel(0x0a0a0a0a, &mctl_ctl
->zqdr
[2]);
226 for (i
= 0; i
< 6; i
++) {
227 u8 zq
= (CONFIG_DRAM_ZQ
>> (i
* 4)) & 0xf;
229 writel((zq
<< 20) | (zq
<< 16) | (zq
<< 12) |
230 (zq
<< 8) | (zq
<< 4) | (zq
<< 0),
233 writel(PIR_CLRSR
, &mctl_ctl
->pir
);
234 mctl_phy_init(PIR_ZCAL
);
236 zq_val
[i
] = readl(&mctl_ctl
->zqdr
[0]) & 0xff;
237 writel(REPEAT_BYTE(zq_val
[i
]), &mctl_ctl
->zqdr
[2]);
239 writel(PIR_CLRSR
, &mctl_ctl
->pir
);
240 mctl_phy_init(PIR_ZCAL
);
242 val
= readl(&mctl_ctl
->zqdr
[0]) >> 24;
243 zq_val
[i
] |= bin_to_mgray(mgray_to_bin(val
) - 1) << 8;
246 writel((zq_val
[1] << 16) | zq_val
[0], &mctl_ctl
->zqdr
[0]);
247 writel((zq_val
[3] << 16) | zq_val
[2], &mctl_ctl
->zqdr
[1]);
248 writel((zq_val
[5] << 16) | zq_val
[4], &mctl_ctl
->zqdr
[2]);
251 static void mctl_set_cr(struct dram_para
*para
)
253 struct sunxi_mctl_com_reg
* const mctl_com
=
254 (struct sunxi_mctl_com_reg
*)SUNXI_DRAM_COM_BASE
;
256 writel(MCTL_CR_BL8
| MCTL_CR_2T
| MCTL_CR_DDR3
| MCTL_CR_INTERLEAVED
|
257 MCTL_CR_EIGHT_BANKS
| MCTL_CR_BUS_WIDTH(para
->bus_width
) |
258 (para
->dual_rank
? MCTL_CR_DUAL_RANK
: MCTL_CR_SINGLE_RANK
) |
259 MCTL_CR_PAGE_SIZE(para
->page_size
) |
260 MCTL_CR_ROW_BITS(para
->row_bits
), &mctl_com
->cr
);
263 static void mctl_sys_init(struct dram_para
*para
)
265 struct sunxi_ccm_reg
* const ccm
=
266 (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
267 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
268 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
270 clrbits_le32(&ccm
->mbus0_clk_cfg
, MBUS_CLK_GATE
);
271 clrbits_le32(&ccm
->mbus_reset
, CCM_MBUS_RESET_RESET
);
272 clrbits_le32(&ccm
->ahb_gate0
, 1 << AHB_GATE_OFFSET_MCTL
);
273 clrbits_le32(&ccm
->ahb_reset0_cfg
, 1 << AHB_RESET_OFFSET_MCTL
);
274 clrbits_le32(&ccm
->pll5_cfg
, CCM_PLL5_CTRL_EN
);
277 clrbits_le32(&ccm
->dram_clk_cfg
, CCM_DRAMCLK_CFG_RST
);
280 clock_set_pll5(CONFIG_DRAM_CLK
* 2 * 1000000, false);
281 clrsetbits_le32(&ccm
->dram_clk_cfg
,
282 CCM_DRAMCLK_CFG_DIV_MASK
| CCM_DRAMCLK_CFG_SRC_MASK
,
283 CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5
|
284 CCM_DRAMCLK_CFG_UPD
);
285 mctl_await_completion(&ccm
->dram_clk_cfg
, CCM_DRAMCLK_CFG_UPD
, 0);
287 setbits_le32(&ccm
->ahb_reset0_cfg
, 1 << AHB_RESET_OFFSET_MCTL
);
288 setbits_le32(&ccm
->ahb_gate0
, 1 << AHB_GATE_OFFSET_MCTL
);
289 setbits_le32(&ccm
->mbus_reset
, CCM_MBUS_RESET_RESET
);
290 setbits_le32(&ccm
->mbus0_clk_cfg
, MBUS_CLK_GATE
);
292 setbits_le32(&ccm
->dram_clk_cfg
, CCM_DRAMCLK_CFG_RST
);
295 writel(0xc00e, &mctl_ctl
->clken
);
299 static int mctl_channel_init(struct dram_para
*para
)
301 struct sunxi_mctl_com_reg
* const mctl_com
=
302 (struct sunxi_mctl_com_reg
*)SUNXI_DRAM_COM_BASE
;
303 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
304 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
309 mctl_set_timing_params(para
);
310 mctl_set_master_priority();
312 /* setting VTC, default disable all VT */
313 clrbits_le32(&mctl_ctl
->pgcr
[0], (1 << 30) | 0x3f);
314 clrsetbits_le32(&mctl_ctl
->pgcr
[1], 1 << 24, 1 << 26);
316 /* increase DFI_PHY_UPD clock */
317 writel(PROTECT_MAGIC
, &mctl_com
->protect
);
319 clrsetbits_le32(&mctl_ctl
->upd2
, 0xfff << 16, 0x50 << 16);
320 writel(0x0, &mctl_com
->protect
);
324 for (i
= 0; i
< 4; i
++)
325 clrsetbits_le32(&mctl_ctl
->datx
[i
].gcr
, (0x3 << 4) |
326 (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
328 IS_ENABLED(CONFIG_DRAM_ODT_EN
) ? 0x0 : 0x2);
330 /* AC PDR should always ON */
331 setbits_le32(&mctl_ctl
->aciocr
, 0x1 << 1);
333 /* set DQS auto gating PD mode */
334 setbits_le32(&mctl_ctl
->pgcr
[2], 0x3 << 6);
336 /* dx ddr_clk & hdr_clk dynamic mode */
337 clrbits_le32(&mctl_ctl
->pgcr
[0], (0x3 << 14) | (0x3 << 12));
339 /* dphy & aphy phase select 270 degree */
340 clrsetbits_le32(&mctl_ctl
->pgcr
[2], (0x3 << 10) | (0x3 << 8),
341 (0x1 << 10) | (0x2 << 8));
344 if (para
->bus_width
!= 32) {
345 writel(0x0, &mctl_ctl
->datx
[2].gcr
);
346 writel(0x0, &mctl_ctl
->datx
[3].gcr
);
349 /* data training configuration */
350 clrsetbits_le32(&mctl_ctl
->dtcr
, 0xf << 24,
351 (para
->dual_rank
? 0x3 : 0x1) << 24);
354 if (para
->read_delays
|| para
->write_delays
) {
355 mctl_dq_delay(para
->read_delays
, para
->write_delays
);
359 mctl_zq_calibration(para
);
361 mctl_phy_init(PIR_PLLINIT
| PIR_DCAL
| PIR_PHYRST
| PIR_DRAMRST
|
362 PIR_DRAMINIT
| PIR_QSGATE
);
364 /* detect ranks and bus width */
365 if (readl(&mctl_ctl
->pgsr
[0]) & (0xfe << 20)) {
367 if (((readl(&mctl_ctl
->datx
[0].gsr
[0]) >> 24) & 0x2) ||
368 ((readl(&mctl_ctl
->datx
[1].gsr
[0]) >> 24) & 0x2)) {
369 clrsetbits_le32(&mctl_ctl
->dtcr
, 0xf << 24, 0x1 << 24);
373 /* only half DQ width */
374 if (((readl(&mctl_ctl
->datx
[2].gsr
[0]) >> 24) & 0x1) ||
375 ((readl(&mctl_ctl
->datx
[3].gsr
[0]) >> 24) & 0x1)) {
376 writel(0x0, &mctl_ctl
->datx
[2].gcr
);
377 writel(0x0, &mctl_ctl
->datx
[3].gcr
);
378 para
->bus_width
= 16;
385 mctl_phy_init(PIR_QSGATE
);
386 if (readl(&mctl_ctl
->pgsr
[0]) & (0xfe << 20))
390 /* check the dramc status */
391 mctl_await_completion(&mctl_ctl
->statr
, 0x1, 0x1);
393 /* liuke added for refresh debug */
394 setbits_le32(&mctl_ctl
->rfshctl0
, 0x1 << 31);
396 clrbits_le32(&mctl_ctl
->rfshctl0
, 0x1 << 31);
399 /* set PGCR3, CKE polarity */
400 writel(0x00aa0060, &mctl_ctl
->pgcr
[3]);
402 /* power down zq calibration module for power save */
403 setbits_le32(&mctl_ctl
->zqcr
, ZQCR_PWRDOWN
);
405 /* enable master access */
406 writel(0xffffffff, &mctl_com
->maer
);
411 static void mctl_auto_detect_dram_size(struct dram_para
*para
)
413 /* detect row address bits */
414 para
->page_size
= 512;
418 for (para
->row_bits
= 11; para
->row_bits
< 16; para
->row_bits
++)
419 if (mctl_mem_matches((1 << (para
->row_bits
+ 3)) * para
->page_size
))
422 /* detect page size */
423 para
->page_size
= 8192;
426 for (para
->page_size
= 512; para
->page_size
< 8192; para
->page_size
*= 2)
427 if (mctl_mem_matches(para
->page_size
))
431 unsigned long sunxi_dram_init(void)
433 struct sunxi_mctl_com_reg
* const mctl_com
=
434 (struct sunxi_mctl_com_reg
*)SUNXI_DRAM_COM_BASE
;
435 struct sunxi_mctl_ctl_reg
* const mctl_ctl
=
436 (struct sunxi_mctl_ctl_reg
*)SUNXI_DRAM_CTL0_BASE
;
438 struct dram_para para
= {
439 .read_delays
= 0x00007979, /* dram_tpr12 */
440 .write_delays
= 0x6aaa0000, /* dram_tpr11 */
447 mctl_sys_init(¶
);
448 if (mctl_channel_init(¶
))
452 writel(0x00000303, &mctl_ctl
->odtmap
);
454 writel(0x00000201, &mctl_ctl
->odtmap
);
458 writel(0x0c000400, &mctl_ctl
->odtcfg
);
460 /* clear credit value */
461 setbits_le32(&mctl_com
->cccr
, 1 << 31);
464 mctl_auto_detect_dram_size(¶
);
467 return (1 << (para
.row_bits
+ 3)) * para
.page_size
*
468 (para
.dual_rank
? 2 : 1);