arch/arm/cpu/armv7m/stm32f4/clock.c

   1 /*
   2  * (C) Copyright 2015
   3  * Kamil Lulko, <rev13@wp.pl>
   4  *
   5  * (C) Copyright 2014
   6  * STMicroelectronics
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/stm32.h>
  14
  15 #define RCC_CR_HSION            (1 << 0)
  16 #define RCC_CR_HSEON            (1 << 16)
  17 #define RCC_CR_HSERDY           (1 << 17)
  18 #define RCC_CR_HSEBYP           (1 << 18)
  19 #define RCC_CR_CSSON            (1 << 19)
  20 #define RCC_CR_PLLON            (1 << 24)
  21 #define RCC_CR_PLLRDY           (1 << 25)
  22
  23 #define RCC_PLLCFGR_PLLM_MASK   0x3F
  24 #define RCC_PLLCFGR_PLLN_MASK   0x7FC0
  25 #define RCC_PLLCFGR_PLLP_MASK   0x30000
  26 #define RCC_PLLCFGR_PLLQ_MASK   0xF000000
  27 #define RCC_PLLCFGR_PLLSRC      (1 << 22)
  28 #define RCC_PLLCFGR_PLLN_SHIFT  6
  29 #define RCC_PLLCFGR_PLLP_SHIFT  16
  30 #define RCC_PLLCFGR_PLLQ_SHIFT  24
  31
  32 #define RCC_CFGR_AHB_PSC_MASK   0xF0
  33 #define RCC_CFGR_APB1_PSC_MASK  0x1C00
  34 #define RCC_CFGR_APB2_PSC_MASK  0xE000
  35 #define RCC_CFGR_SW0            (1 << 0)
  36 #define RCC_CFGR_SW1            (1 << 1)
  37 #define RCC_CFGR_SW_MASK        0x3
  38 #define RCC_CFGR_SW_HSI         0
  39 #define RCC_CFGR_SW_HSE         RCC_CFGR_SW0
  40 #define RCC_CFGR_SW_PLL         RCC_CFGR_SW1
  41 #define RCC_CFGR_SWS0           (1 << 2)
  42 #define RCC_CFGR_SWS1           (1 << 3)
  43 #define RCC_CFGR_SWS_MASK       0xC
  44 #define RCC_CFGR_SWS_HSI        0
  45 #define RCC_CFGR_SWS_HSE        RCC_CFGR_SWS0
  46 #define RCC_CFGR_SWS_PLL        RCC_CFGR_SWS1
  47 #define RCC_CFGR_HPRE_SHIFT     4
  48 #define RCC_CFGR_PPRE1_SHIFT    10
  49 #define RCC_CFGR_PPRE2_SHIFT    13
  50
  51 #define RCC_APB1ENR_PWREN       (1 << 28)
  52
  53 #define PWR_CR_VOS0             (1 << 14)
  54 #define PWR_CR_VOS1             (1 << 15)
  55 #define PWR_CR_VOS_MASK         0xC000
  56 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
  57 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
  58 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
  59
  60 #define FLASH_ACR_WS(n)         n
  61 #define FLASH_ACR_PRFTEN        (1 << 8)
  62 #define FLASH_ACR_ICEN          (1 << 9)
  63 #define FLASH_ACR_DCEN          (1 << 10)
  64
  65 struct pll_psc {
  66         u8      pll_m;
  67         u16     pll_n;
  68         u8      pll_p;
  69         u8      pll_q;
  70         u8      ahb_psc;
  71         u8      apb1_psc;
  72         u8      apb2_psc;
  73 };
  74
  75 #define AHB_PSC_1               0
  76 #define AHB_PSC_2               0x8
  77 #define AHB_PSC_4               0x9
  78 #define AHB_PSC_8               0xA
  79 #define AHB_PSC_16              0xB
  80 #define AHB_PSC_64              0xC
  81 #define AHB_PSC_128             0xD
  82 #define AHB_PSC_256             0xE
  83 #define AHB_PSC_512             0xF
  84
  85 #define APB_PSC_1               0
  86 #define APB_PSC_2               0x4
  87 #define APB_PSC_4               0x5
  88 #define APB_PSC_8               0x6
  89 #define APB_PSC_16              0x7
  90
  91 #if !defined(CONFIG_STM32_HSE_HZ)
  92 #error "CONFIG_STM32_HSE_HZ not defined!"
  93 #else
  94 #if (CONFIG_STM32_HSE_HZ == 8000000)
  95 #if (CONFIG_SYS_CLK_FREQ == 180000000)
  96 /* 180 MHz */
  97 struct pll_psc sys_pll_psc = {
  98         .pll_m = 8,
  99         .pll_n = 360,
 100         .pll_p = 2,
 101         .pll_q = 8,
 102         .ahb_psc = AHB_PSC_1,
 103         .apb1_psc = APB_PSC_4,
 104         .apb2_psc = APB_PSC_2
 105 };
 106 #else
 107 /* default 168 MHz */
 108 struct pll_psc sys_pll_psc = {
 109         .pll_m = 8,
 110         .pll_n = 336,
 111         .pll_p = 2,
 112         .pll_q = 7,
 113         .ahb_psc = AHB_PSC_1,
 114         .apb1_psc = APB_PSC_4,
 115         .apb2_psc = APB_PSC_2
 116 };
 117 #endif
 118 #else
 119 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
 120 #endif
 121 #endif
 122
 123 int configure_clocks(void)
 124 {
 125         /* Reset RCC configuration */
 126         setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
 127         writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
 128         clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 129                 | RCC_CR_PLLON));
 130         writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
 131         clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
 132         writel(0, &STM32_RCC->cir); /* Disable all interrupts */
 133
 134         /* Configure for HSE+PLL operation */
 135         setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
 136         while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
 137                 ;
 138
 139         /* Enable high performance mode, System frequency up to 180 MHz */
 140         setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
 141         writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
 142
 143         setbits_le32(&STM32_RCC->cfgr, ((
 144                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 145                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 146                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 147
 148         writel(sys_pll_psc.pll_m
 149                 | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
 150                 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
 151                 | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
 152                 &STM32_RCC->pllcfgr);
 153         setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
 154
 155         setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
 156
 157         while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
 158                 ;
 159
 160         /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
 161         writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
 162                 | FLASH_ACR_DCEN, &STM32_FLASH->acr);
 163
 164         clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 165         setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 166
 167         while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
 168                         RCC_CFGR_SWS_PLL)
 169                 ;
 170
 171         return 0;
 172 }
 173
 174 unsigned long clock_get(enum clock clck)
 175 {
 176         u32 sysclk = 0;
 177         u32 shift = 0;
 178         /* Prescaler table lookups for clock computation */
 179         u8 ahb_psc_table[16] = {
 180                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 181         };
 182         u8 apb_psc_table[8] = {
 183                 0, 0, 0, 0, 1, 2, 3, 4
 184         };
 185
 186         if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
 187                         RCC_CFGR_SWS_PLL) {
 188                 u16 pllm, plln, pllp;
 189                 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 190                 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 191                         >> RCC_PLLCFGR_PLLN_SHIFT);
 192                 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 193                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 194                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 195         }
 196
 197         switch (clck) {
 198         case CLOCK_CORE:
 199                 return sysclk;
 200                 break;
 201         case CLOCK_AHB:
 202                 shift = ahb_psc_table[(
 203                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 204                         >> RCC_CFGR_HPRE_SHIFT)];
 205                 return sysclk >>= shift;
 206                 break;
 207         case CLOCK_APB1:
 208                 shift = apb_psc_table[(
 209                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 210                         >> RCC_CFGR_PPRE1_SHIFT)];
 211                 return sysclk >>= shift;
 212                 break;
 213         case CLOCK_APB2:
 214                 shift = apb_psc_table[(
 215                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 216                         >> RCC_CFGR_PPRE2_SHIFT)];
 217                 return sysclk >>= shift;
 218                 break;
 219         default:
 220                 return 0;
 221                 break;
 222         }
 223 }