arch/arm/cpu/armv8/fsl-layerscape/Kconfig

   1 config ARCH_LS1012A
   2         bool
   3         select FSL_LSCH2
   4         select SYS_FSL_DDR_BE
   5         select SYS_FSL_MMDC
   6         select SYS_FSL_ERRATUM_A010315
   7
   8 config ARCH_LS1043A
   9         bool
  10         select FSL_LSCH2
  11         select SYS_FSL_DDR_BE
  12         select SYS_FSL_DDR_VER_50
  13         select SYS_FSL_ERRATUM_A010315
  14         select SYS_FSL_ERRATUM_A010539
  15
  16 config ARCH_LS1046A
  17         bool
  18         select FSL_LSCH2
  19         select SYS_FSL_DDR_BE
  20         select SYS_FSL_DDR4
  21         select SYS_FSL_DDR_VER_50
  22         select SYS_FSL_ERRATUM_A010539
  23         select SYS_FSL_SRDS_2
  24
  25 config ARCH_LS2080A
  26         bool
  27         select FSL_LSCH3
  28         select SYS_FSL_DDR4
  29         select SYS_FSL_DDR_LE
  30         select SYS_FSL_DDR_VER_50
  31         select SYS_FSL_HAS_DP_DDR
  32         select SYS_FSL_SRDS_2
  33
  34 config FSL_LSCH2
  35         bool
  36         select SYS_FSL_SRDS_1
  37         select SYS_HAS_SERDES
  38
  39 config FSL_LSCH3
  40         bool
  41         select SYS_FSL_SRDS_1
  42         select SYS_HAS_SERDES
  43
  44 menu "Layerscape architecture"
  45         depends on FSL_LSCH2 || FSL_LSCH3
  46
  47 config SYS_FSL_MMDC
  48         bool
  49
  50 config SYS_FSL_ERRATUM_A010315
  51         bool "Workaround for PCIe erratum A010315"
  52
  53 config SYS_FSL_ERRATUM_A010539
  54         bool "Workaround for PIN MUX erratum A010539"
  55
  56 config MAX_CPUS
  57         int "Maximum number of CPUs permitted for Layerscape"
  58         default 4 if ARCH_LS1043A
  59         default 4 if ARCH_LS1046A
  60         default 16 if ARCH_LS2080A
  61         default 1
  62         help
  63           Set this number to the maximum number of possible CPUs in the SoC.
  64           SoCs may have multiple clusters with each cluster may have multiple
  65           ports. If some ports are reserved but higher ports are used for
  66           cores, count the reserved ports. This will allocate enough memory
  67           in spin table to properly handle all cores.
  68
  69 config NUM_DDR_CONTROLLERS
  70         int "Maximum DDR controllers"
  71         default 3 if ARCH_LS2080A
  72         default 1
  73
  74 config SECURE_BOOT
  75         bool
  76         help
  77                 Enable Freescale Secure Boot feature
  78
  79 config QSPI_AHB_INIT
  80         bool "Init the QSPI AHB bus"
  81         help
  82           The default setting for QSPI AHB bus just support 3bytes addressing.
  83           But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
  84           bus for those flashes to support the full QSPI flash size.
  85
  86 config SYS_FSL_IFC_BANK_COUNT
  87         int "Maximum banks of Integrated flash controller"
  88         depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
  89         default 4 if ARCH_LS1043A
  90         default 4 if ARCH_LS1046A
  91         default 8 if ARCH_LS2080A
  92
  93 config SYS_FSL_HAS_DP_DDR
  94         bool
  95
  96 config SYS_FSL_SRDS_1
  97         bool
  98
  99 config SYS_FSL_SRDS_2
 100         bool
 101
 102 config SYS_HAS_SERDES
 103         bool
 104
 105 config SYS_FSL_DDR
 106         bool "Freescale DDR driver"
 107         help
 108           Select Freescale General DDR driver, shared between most Freescale
 109           PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
 110           based Layerscape SoCs (such as ls2080a).
 111
 112 config SYS_FSL_DDR_BE
 113         bool
 114         help
 115           Access DDR registers in big-endian.
 116
 117 config SYS_FSL_DDR_LE
 118         bool
 119         help
 120           Access DDR registers in little-endian.
 121
 122 config SYS_FSL_DDR_VER
 123         int
 124         default 50 if SYS_FSL_DDR_VER_50
 125
 126 config SYS_FSL_DDR_VER_50
 127         bool
 128
 129 config SYS_FSL_DDRC_ARM_GEN3
 130         bool
 131
 132 config SYS_FSL_DDRC_GEN4
 133         bool
 134
 135 config SYS_FSL_DDR3
 136         bool "Freescale DDR3 controller"
 137         depends on !SYS_FSL_DDR4
 138         select SYS_FSL_DDR
 139         select SYS_FSL_DDRC_ARM_GEN3
 140         help
 141           Enable Freescale DDR3 controller on ARM-based SoCs.
 142
 143 config SYS_FSL_DDR4
 144         bool "Freescale DDR4 controller"
 145         select SYS_FSL_DDR
 146         select SYS_FSL_DDRC_GEN4
 147         help
 148           Enable Freescale DDR4 controller.
 149
 150 endmenu