2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
12 #include <fsl-mc/ldpaa_wriop.h>
14 #ifdef CONFIG_SYS_FSL_SRDS_1
15 static u8 serdes1_prtcl_map
[SERDES_PRCTL_COUNT
];
17 #ifdef CONFIG_SYS_FSL_SRDS_2
18 static u8 serdes2_prtcl_map
[SERDES_PRCTL_COUNT
];
21 #ifdef CONFIG_FSL_MC_ENET
22 int xfi_dpmac
[XFI8
+ 1];
23 int sgmii_dpmac
[SGMII16
+ 1];
26 int is_serdes_configured(enum srds_prtcl device
)
30 #ifdef CONFIG_SYS_FSL_SRDS_1
31 ret
|= serdes1_prtcl_map
[device
];
33 #ifdef CONFIG_SYS_FSL_SRDS_2
34 ret
|= serdes2_prtcl_map
[device
];
40 int serdes_get_first_lane(u32 sd
, enum srds_prtcl device
)
42 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
43 u32 cfg
= gur_in32(&gur
->rcwsr
[28]);
47 #ifdef CONFIG_SYS_FSL_SRDS_1
49 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
;
50 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
;
53 #ifdef CONFIG_SYS_FSL_SRDS_2
55 cfg
&= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
;
56 cfg
>>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
;
60 printf("invalid SerDes%d\n", sd
);
63 /* Is serdes enabled at all? */
67 for (i
= 0; i
< SRDS_MAX_LANES
; i
++) {
68 if (serdes_get_prtcl(sd
, cfg
, i
) == device
)
75 void serdes_init(u32 sd
, u32 sd_addr
, u32 sd_prctl_mask
, u32 sd_prctl_shift
,
76 u8 serdes_prtcl_map
[SERDES_PRCTL_COUNT
])
78 struct ccsr_gur __iomem
*gur
= (void *)(CONFIG_SYS_FSL_GUTS_ADDR
);
82 memset(serdes_prtcl_map
, 0, sizeof(u8
) * SERDES_PRCTL_COUNT
);
84 cfg
= gur_in32(&gur
->rcwsr
[28]) & sd_prctl_mask
;
85 cfg
>>= sd_prctl_shift
;
86 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd
+ 1, cfg
, cfg
);
88 if (!is_serdes_prtcl_valid(sd
, cfg
))
89 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd
+ 1, cfg
);
91 for (lane
= 0; lane
< SRDS_MAX_LANES
; lane
++) {
92 enum srds_prtcl lane_prtcl
= serdes_get_prtcl(sd
, cfg
, lane
);
93 if (unlikely(lane_prtcl
>= SERDES_PRCTL_COUNT
))
94 debug("Unknown SerDes lane protocol %d\n", lane_prtcl
);
96 serdes_prtcl_map
[lane_prtcl
] = 1;
97 #ifdef CONFIG_FSL_MC_ENET
100 wriop_init_dpmac(sd
, 5, (int)lane_prtcl
);
101 wriop_init_dpmac(sd
, 6, (int)lane_prtcl
);
102 wriop_init_dpmac(sd
, 7, (int)lane_prtcl
);
103 wriop_init_dpmac(sd
, 8, (int)lane_prtcl
);
106 wriop_init_dpmac(sd
, 1, (int)lane_prtcl
);
107 wriop_init_dpmac(sd
, 2, (int)lane_prtcl
);
108 wriop_init_dpmac(sd
, 3, (int)lane_prtcl
);
109 wriop_init_dpmac(sd
, 4, (int)lane_prtcl
);
112 wriop_init_dpmac(sd
, 13, (int)lane_prtcl
);
113 wriop_init_dpmac(sd
, 14, (int)lane_prtcl
);
114 wriop_init_dpmac(sd
, 15, (int)lane_prtcl
);
115 wriop_init_dpmac(sd
, 16, (int)lane_prtcl
);
118 wriop_init_dpmac(sd
, 9, (int)lane_prtcl
);
119 wriop_init_dpmac(sd
, 10, (int)lane_prtcl
);
120 wriop_init_dpmac(sd
, 11, (int)lane_prtcl
);
121 wriop_init_dpmac(sd
, 12, (int)lane_prtcl
);
124 if (lane_prtcl
>= XFI1
&& lane_prtcl
<= XFI8
)
126 xfi_dpmac
[lane_prtcl
],
129 if (lane_prtcl
>= SGMII1
&&
130 lane_prtcl
<= SGMII16
)
131 wriop_init_dpmac(sd
, sgmii_dpmac
[
141 void fsl_serdes_init(void)
143 #ifdef CONFIG_FSL_MC_ENET
146 for (i
= XFI1
, j
= 1; i
<= XFI8
; i
++, j
++)
149 for (i
= SGMII1
, j
= 1; i
<= SGMII16
; i
++, j
++)
153 #ifdef CONFIG_SYS_FSL_SRDS_1
154 serdes_init(FSL_SRDS_1
,
155 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
,
156 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
,
157 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
,
160 #ifdef CONFIG_SYS_FSL_SRDS_2
161 serdes_init(FSL_SRDS_2
,
162 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
+ FSL_SRDS_2
* 0x10000,
163 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
,
164 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
,